DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the COUNTRY OF JAPAN on 06/21/2022.
Election/Restrictions
Applicant's election without traverse of “Species IV (Claims 1-5, 7-11, 13, 15-18, and 20)” in the reply filed on November 24, 2025, is acknowledged.
Claims 6, 12, 14, and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 15-18, and 20 are rejected under 35 U.S.C. 103 as being obvious over US 2022/0093644 A1; Sharangpani et al.; 03/2022; (“644”) in view of US 2017/0358590 A1; Kang et al.; 12/2017; (“590”).
Regarding Claim 1. 644 teaches in Figs. 39A and 39B about a semiconductor memory device, comprising:
a substrate (Fig. 39A, item 10) including a first region (Fig. 39B, item 100) and a second region (Fig. 39B, item 300) arranged in a first direction (Figs. 39A or 39B, right to left);
a plurality of conductive layers (Fig. 39A, items 46) stacked in a stacking direction intersecting with a surface of the substrate (Fig. 39A, layer items 46 are stacked in a vertical direction perpendicular to the surface of the substrate), and extending in the first direction across the first region and the second region (Fig. 39A, layer items 46 extend across first and second regions);
a semiconductor layer (Fig. 39A, item 601) disposed in the first region, extending in the stacking direction, and opposed to the plurality of conductive layers (Fig. 39A, item 601 is within the first region, extending in the stacking direction, and perpendicular to the layer items 46);
an electric charge accumulating film (Fig. 39A, item 50) disposed between the plurality of conductive layers and the semiconductor layer (Fig. 39A, item 50 is disposed between layer items 46 and layer item 601);
a plurality of contact electrodes disposed (Fig. 39A, items 86) in the second region, and connected to a plurality of terrace portions (Fig. 39A, terrace portions of layer items 46, within the second region connected to electrode items 86) of the plurality of conductive layers arranged in the first direction via parts of outer edges of the plurality of conductive layers when viewed from the stacking direction (Fig. 39A, the plurality layer items 46 connect to electrode items 86 via parts of outer edges, resembling a staircase structure when view from the stacking direction); and
a plurality of insulating members (Fig. 39A, items 20) disposed in the second region, and including outer peripheral surfaces surrounded by at least a part of the plurality of conductive layers (Fig. 39A, items 20 include an outer peripheral surface at least partially surrounded by a part of the plurality of item layers 46) when viewed from the stacking direction, wherein
the plurality of insulating members include:
a second insulating member that does not overlap with any of the plurality of contact electrodes (Fig. 39A, items 20 do not overlap with any of the electrode items 86) when viewed from the stacking direction,
a surface on one side in the stacking direction of the first contact electrode includes a contact surface in contact with a first conductive layer of the plurality of conductive layers (Fig. 39A, bottom surface of a first electrode item 86 is in contact with a first layer item 46 of the plurality of layer items 46), and
insides of surfaces surrounding the second insulating member of at least a part of the plurality of conductive layers when viewed from the stacking direction are not provided with a conductive member or a semiconductor member (Fig. 39A, insides of surfaces surrounding items 20 of at least a part of the plurality of layer items 46 provide a dielectric layer item 44, which is neither a semiconductor member nor a conductive member).
644 does not teach about a semiconductor memory device, comprising:
a first insulating member that overlaps with a first contact electrode of the plurality of contact electrodes when viewed from the stacking direction; and
a surface on one side in the stacking direction of the first contact electrode includes a contact surface in contact with the first insulating member.
590 teaches in Fig. 2N about a semiconductor memory device, comprising:
a first insulating member (item 302) that overlaps with a first contact electrode (item 302 overlaps with item MCT) of the plurality of contact electrodes when viewed from the stacking direction; and
a surface on one side in the stacking direction of the first contact electrode includes a contact surface in contact with the first insulating member (bottom surface of item MCT includes a contact surface in contact with item 302).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the first insulating member overlapping and in contact with a first contact electrode when viewed from the stacking direction of 590 to provide support within the second region in 644 in order to “support portion 302 of a lower side of the upper surface of
the contact plug landing portions” as taught by 590 in Fig. 2N and [0055], Ln. 19-20.
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Fig. 39A, annotated by Examiner from Sharangpani et al., “644”
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Fig. 2N, annotated by Examiner from Kang et al., “590”
Regarding Claim 2. 590 teaches in Fig. 2N about a semiconductor memory device, comprising:
a center position of the first contact electrode in cross-sectional surface perpendicular to the stacking direction and including the first contact electrode is a first center position (a center position in a horizontal cross-sectional surface of the electrode item MCT is a center position),
a center position of the first insulating member in cross-sectional surface perpendicular to the stacking direction, and including the first insulating member and one of the plurality of conductive layers surrounding an outer peripheral surface of the first insulating member is a second center position (a center position in a horizontal cross-sectional surface of the item 302 is a center position), and
the first center position does overlap with the second center position when viewed from the stacking direction.
590 does not teach about a semiconductor memory device, comprising:
the first center position does not overlap with the second center position when viewed from the stacking direction.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the first and second center positions to accommodate for any structural support requirements or interface landing requirements, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 3. 590 teaches in Fig. 2N about a semiconductor memory device, comprising:
a length in the first direction of the surface on the one side in the stacking direction of the first contact electrode is a first length (a length in the first direction on a horizontal bottom surface of the electrode item MCT is a first length),
a length in the first direction of the first insulating member at a position in the stacking direction corresponding to a conductive layer that is closest to the first contact electrode among the plurality of conductive layers surrounding an outer peripheral surface of the first insulating member is a second length (a length in the first direction on a horizontal top surface of item 302, that is closest to the electrode item MCT, is a second length), and
the first length is larger than the second length (the horizontal length of the bottom surface of item MCT is larger than the horizontal length of the top surface of item 302).
Regarding Claim 4. 590 teaches in Fig. 2N about a semiconductor memory device, comprising:
the plurality of insulating members includes only a first insulating member that overlaps with the first contact electrode when viewed from the stacking direction.
590 does not teach about a semiconductor memory device, comprising:
the plurality of insulating members further include a third insulating member that overlaps with the first contact electrode when viewed from the stacking direction.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add a third insulating member that also overlaps with the contact item MCT and duplicates the support function similar to the first insulating member, for additional structural support, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
Regarding Claim 5. 590 teaches in Fig. 2N about a semiconductor memory device, comprising:
the surface on the one side in the stacking direction of the first contact electrode does not further includes a contact surface in contact with the third insulating member.
590 does not teach about a semiconductor memory device, comprising:
the surface on the one side in the stacking direction of the first contact electrode further includes a contact surface in contact with the third insulating member.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add a third insulating member that also overlaps with the contact item MCT and duplicates the support function similar to the first insulating member, for additional structural support, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
Regarding Claim 7. 644 teaches in Fig. 39A about a semiconductor memory device, comprising:
a high-dielectric-constant insulating layer (layer item 44) disposed between at least a part of the plurality of conductive layers and one of the plurality of insulating members (layer item 44 is disposed between layer items 46 and insulating members item 20).
Regarding Claim 8. 644 teaches in Figs. 39A and 39B about a semiconductor memory device, comprising:
a substrate (Fig. 39A, item 10) including a first region (Fig. 39B, item 100) and a second region (Fig. 39B, item 300) arranged in a first direction (Figs. 39A or 39B, right to left);
a plurality of conductive layers (Fig. 39A, items 46) stacked in a stacking direction intersecting with a surface of the substrate (Fig. 39A, layer items 46 are stacked in a vertical direction perpendicular to the surface of the substrate), and extending in the first direction across the first region and the second region (Fig. 39A, layer items 46 extend across first and second regions);
a semiconductor layer (Fig. 39A, item 601) disposed in the first region, extending in the stacking direction, and opposed to the plurality of conductive layers (Fig. 39A, item 601 is within the first region, extending in the stacking direction, and perpendicular to the layer items 46);
an electric charge accumulating film (Fig. 39A, item 50) disposed between the plurality of conductive layers and the semiconductor layer (Fig. 39A, item 50 is disposed between layer items 46 and layer item 601);
a plurality of contact electrodes disposed (Fig. 39A, items 86) in the second region, and connected to a plurality of terrace portions (Fig. 39A, terrace portions of layer items 46, within the second region connected to electrode items 86) of the plurality of conductive layers arranged in the first direction via parts of outer edges of the plurality of conductive layers when viewed from the stacking direction (Fig. 39A, the plurality layer items 46 connect to electrode items 86 via parts of outer edges, resembling a staircase structure when view from the stacking direction); and
a plurality of insulating members (Fig. 39A, items 20) disposed in the second region, and including outer peripheral surfaces surrounded by at least a part of the plurality of conductive layers (Fig. 39A, items 20 include an outer peripheral surface at least partially surrounded by a part of the plurality of item layers 46) when viewed from the stacking direction.
644 does not teach about a semiconductor memory device, comprising:
at least two insulating members of the plurality of insulating members overlap with a first contact electrode of the plurality of contact electrodes when viewed from the stacking direction.
590 teaches in Fig. 2N about a semiconductor memory device, comprising:
a first insulating member (item 302) that overlaps with a first contact electrode (item 302 overlaps with item MCT) of the plurality of contact electrodes when viewed from the stacking direction;
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the first insulating member overlapping and in contact with a first contact electrode when viewed from the stacking direction of 590 to provide support within the second region in 644 in order to “support portion 302 of a lower side of the upper surface of
the contact plug landing portions” as taught by 590 in Fig. 2N and [0055], Ln. 19-20.
It would have been also obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add a second insulating member that also overlaps with the contact item MCT and duplicates the support function similar to the first insulating member, for additional structural support, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
Regarding Claim 15. 644 teaches in Fig. 39A about a semiconductor memory device, comprising:
a high-dielectric-constant insulating layer (layer item 44) disposed between at least a part of the plurality of conductive layers and one of the plurality of insulating members (layer item 44 is disposed between layer items 46 and insulating members item 20).
Regarding Claim 16. 644 teaches in Figs. 39A and 39B about a semiconductor memory device, comprising:
a substrate (Fig. 39A, item 10) including a first region (Fig. 39B, item 100) and a second region (Fig. 39B, item 300) arranged in a first direction (Figs. 39A or 39B, right to left);
a plurality of conductive layers (Fig. 39A, items 46) stacked in a stacking direction intersecting with a surface of the substrate (Fig. 39A, layer items 46 are stacked in a vertical direction perpendicular to the surface of the substrate), and extending in the first direction across the first region and the second region (Fig. 39A, layer items 46 extend across first and second regions);
a semiconductor layer (Fig. 39A, item 601) disposed in the first region, extending in the stacking direction, and opposed to the plurality of conductive layers (Fig. 39A, item 601 is within the first region, extending in the stacking direction, and perpendicular to the layer items 46);
an electric charge accumulating film (Fig. 39A, item 50) disposed between the plurality of conductive layers and the semiconductor layer (Fig. 39A, item 50 is disposed between layer items 46 and layer item 601);
a plurality of contact electrodes disposed (Fig. 39A, items 86) in the second region, and connected to a plurality of terrace portions (Fig. 39A, terrace portions of layer items 46, within the second region connected to electrode items 86) of the plurality of conductive layers arranged in the first direction via parts of outer edges of the plurality of conductive layers when viewed from the stacking direction (Fig. 39A, the plurality layer items 46 connect to electrode items 86 via parts of outer edges, resembling a staircase structure when view from the stacking direction); and
a plurality of insulating members (Fig. 39A, items 20) disposed in the second region, and including outer peripheral surfaces surrounded by at least a part of the plurality of conductive layers (Fig. 39A, items 20 include an outer peripheral surface at least partially surrounded by a part of the plurality of item layers 46) when viewed from the stacking direction.
644 does not teach about a semiconductor memory device, wherein
the plurality of insulating members include a first insulating member that overlaps with a first contact electrode of the plurality of contact electrodes when viewed from the stacking direction,
a center position of the first contact electrode in cross-sectional surface perpendicular to the stacking direction and including the first contact electrode is a first center position,
a center position of the first insulating member in cross-sectional surface perpendicular to the stacking direction, and including the first insulating member and one of the plurality of conductive layers surrounding an outer peripheral surface of the first insulating member is a second center position, and
the first center position does not overlap with the second center position when viewed from the stacking direction.
590 teaches in Fig. 2N about a semiconductor memory device, wherein
the plurality of insulating members include a first insulating member (item 302) that overlaps with a first contact electrode (item 302 overlaps with item MCT) of the plurality of contact electrodes when viewed from the stacking direction,
a center position of the first contact electrode in cross-sectional surface perpendicular to the stacking direction and including the first contact electrode is a first center position (a center position in a horizontal cross-sectional surface of the electrode item MCT is a center position),
a center position of the first insulating member in cross-sectional surface perpendicular to the stacking direction, and including the first insulating member and one of the plurality of conductive layers surrounding an outer peripheral surface of the first insulating member is a second center position (a center position in a horizontal cross-sectional surface of the item 302 is a center position), and
the first center position does overlap with the second center position when viewed from the stacking direction.
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the first insulating member overlapping and in contact with a first contact electrode when viewed from the stacking direction of 590 to provide support within the second region in 644 in order to “support portion 302 of a lower side of the upper surface of
the contact plug landing portions” as taught by 590 in Fig. 2N and [0055], Ln. 19-20.
It would have been also obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to define and rearrange the first and second center positions to accommodate for any structural support requirements or interface landing requirements, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 17. 590 teaches in Fig. 2N about a semiconductor memory device, comprising:
a length in the first direction of a surface on a side of the first insulating member in the stacking direction of the first contact electrode is a first length (a length in the first direction on a horizontal bottom surface of the electrode item MCT is a first length),
a length in the first direction of the first insulating member at a position in the stacking direction corresponding to a conductive layer that is closest to the first contact electrode among the plurality of conductive layers surrounding an outer peripheral surface of the first insulating member is a second length (a length in the first direction on a horizontal top surface of item 302, that is closest to the electrode item MCT, is a second length), and
the first length is larger than the second length (the horizontal length of the bottom surface of item MCT is larger than the horizontal length of the top surface of item 302).
Regarding Claim 18. 590 teaches in Fig. 2N about a semiconductor memory device, comprising:
a surface on one side in the stacking direction of the first contact electrode includes a contact surface (bottom contact surface of electrode item MCT) in contact with a first conductive layer (bottom contact surface of electrode item MCT is in contact with conductive layer item 220) of the plurality of conductive layers, and a contact surface in contact with the first insulating member (bottom contact surface of electrode item MCT is in contact with insulating member item 302).
Regarding Claim 20. 644 teaches in Fig. 39A about a semiconductor memory device, comprising:
a high-dielectric-constant insulating layer (layer item 44) disposed between at least a part of the plurality of conductive layers and one of the plurality of insulating members (layer item 44 is disposed between layer items 46 and insulating members item 20).
Allowable Subject Matter
Claims 9-11 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/ Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897