DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: paragraph [0118] recites “the third surface has a larger area than the third surface”, which is likely a typo.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-7 and 9-10 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim(s) 1-7, the claim feature or are dependent upon claims which feature the limitation “the first surface has a smaller area than the second surface in a plane that is substantially perpendicular to the first direction” (claim 1). However, claim 1 also recites “the first surface is over the second surface in the first direction”. It is unclear how the areas of both surfaces can be in one plane perpendicular to the first direction when the surfaces are also separated in the first direction. For the purpose of examination, the examiner interprets the claim as reciting “the first surface has a smaller area than the second surface in [[a]] respective planes that [[is]] are substantially perpendicular to the first direction”.
Regarding claim(s) 4-5, the claim feature or are dependent upon claims which feature the limitation “the third surface has a larger area than the third surface” (claim 4). It is unclear how the third surface could have an area larger than itself. It is the examiner’s opinion that the limitation is likely a typo and should instead recite “the fourth surface has a larger area than the third surface”. However, since the specification similarly recites “the third surface has a larger area than the third surface” (specification paragraph [0118]), the intended language of the limitation is uncertain. Since no clear interpretation of the limitation can be made, for the purpose of examination, no prior art rejection of claims 4-5 is made.
Regarding claims 9-10, claim 9 recites the limitation "the dielectric structure comprising an additional surface opposing the surface" (emphasis added) and claim 10 recites “the dielectric structure comprises nitrogen or carbon at the surface” (emphasis added). There is insufficient antecedent basis for this limitation in the claim. “The surface” may refer to any of “a first surface”, “a second surface”, or “a surface of the dielectric structure”, which are given antecedent basis in claim 8, or another feature altogether. However, it is not clear which feature “the surface” refers to because it lacks the part of the language which distinguishes it from other claimed surfaces. For the purpose of examination, Examiner interprets “the surface” as referring to the aforementioned “surface of the dielectric structure”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6, and 8-14 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Sung et al. (US 10811304 B2, hereinafter S1).
Regarding independent claim 1, S1 discloses in S1 FIG. 10 and associated text An integrated circuit (IC) device, comprising: a first transistor (the structure comprising the following elements on the left side of diffusion break trench 130) comprising a source region (source/drain epitaxial layer 122) and a source contact over the source region in a first direction (S/D contact 154 is over 122 in the vertical direction); a second transistor (the structure comprising the following elements on the right side of diffusion break trench 130) comprising a drain region (source/drain epitaxial layer 122) and a drain contact over the drain region in the first direction (S/D contact 154 is over 122 in the vertical direction); and a dielectric structure (structure in diffusion break trench 130 comprising barrier layer 144 and second ILD 146, which is SiO2 (S1 (39)), a dielectric) between the source region of the first transistor and the drain region of the second transistor in a second direction that is substantially perpendicular to the first direction (the structure in 130 is between the transistors to its left and right, as interpreted above, in a horizontal direction), the dielectric structure comprising a first surface (top surface of 130) and a second surface (bottom surface of 130), wherein: the first surface is over the second surface in the first direction (the top surface of 130 is over its bottom surface in the vertical direction), the first surface is closer to the source contact or the drain contact than the second surface (as shown), and the first surface has a smaller area than the second surface in respective planes that are substantially perpendicular to the first direction (as shown, the top surface of 130 is narrower than the bottom surface, therefore the area of the top surface is interpreted as being smaller than that of the bottom surface within their respective planes).
Regarding dependent claim 2, S1 further discloses in S1 FIG. 10 and associated text The IC device according to claim 1, wherein the dielectric structure comprises: a first structure comprising a first dielectric material (ILD 146 comprises SiO2 (S1 (39))); and a second structure comprising a second dielectric material that is different from the first dielectric material (barrier layer 144 comprises silicon nitride (S1 (38))), wherein the first surface is a surface of the first structure (the top surface of 130 coincides with a surface of 146), and the second surface is a surface of the second structure (the bottom surface of 130 coincides with a surface of 144).
Regarding dependent claim 3, S1 further discloses in S1 FIG. 10 and associated text The IC device according to claim 2, wherein the second dielectric material comprises nitrogen or carbon (barrier layer 144 comprises silicon nitride (S1 (38)), therefore comprises nitrogen).
Regarding dependent claim 6, S1 further discloses in S1 FIG. 10 and associated text The IC device according to claim 1, wherein at least part of the dielectric structure is surrounded by an electrically conductive material (metal 150 is on either side of the structure in 130, therefore the dielectric structure is interpreted as being surrounded by an electrically conductive material).
Regarding independent claim 8, S1 discloses in S1 FIG. 10 and associated text An integrated circuit (IC) device, comprising: a substrate (substrate 102) comprising a first surface (top surface of 102) and a second surface (bottom surface of 102), the second surface opposing the first surface (as shown); a semiconductor structure over the substrate (source/drain epitaxial layer 122 is interpreted as a semiconductor structure), wherein the semiconductor structure is closer to the first surface than the second surface (as shown), and a longitudinal axis of the semiconductor structure is along a first direction (the longitudinal axis of 122 is interpreted as corresponding to the horizontal direction); and a dielectric structure at least partially in the substrate (the structure in diffusion break trench 130 comprising barrier layer 144 and second ILD 146, which is SiO2 (S1 (39)), a dielectric, is partially in 102), wherein: a longitudinal axis of the dielectric structure is along a second direction that is substantially perpendicular to the first direction (the longitudinal axis of 130 is interpreted as corresponding to the vertical direction), and a surface of the dielectric structure is closer to the second surface than the first surface (the bottom surface of 130 is closer to the bottom surface of 102 than the top surface of 102).
Regarding dependent claim 9, S1 further discloses in S1 FIG. 10 and associated text The IC device according to claim 8, wherein: the dielectric structure comprising an additional surface opposing the surface (the top surface of 130 opposes the bottom surface of 130), the second surface is closer to the surface than the additional surface (the bottom surface of 130 is closer to the bottom surface of 102 than the top surface of 102, as shown), and the surface is larger than the additional surface (the bottom surface of 130 is wider than its top surface, therefore interpreted as larger).
Regarding dependent claim 10, S1 further discloses in S1 FIG. 10 and associated text The IC device according to claim 9, wherein the dielectric structure comprises nitrogen or carbon at the surface (barrier layer 144 is at the bottom surface of 130 and comprises silicon nitride (S1 (38)), therefore nitrogen).
Regarding dependent claim 11, S1 further discloses in S1 FIG. 10 and associated text The IC device according to claim 8, wherein a first portion of the semiconductor structure is a source region or drain region of a first transistor (the part of S/D epitaxial layer 122 left of 130 is interpreted as the first portion), and a second portion of the semiconductor structure is a source region or drain region of a second transistor (the part of S/D epitaxial layer 122 right of 130 is interpreted as the second portion).
Regarding dependent claim 12, S1 further discloses in S1 FIG. 10 and associated text The IC device according to claim 11, wherein the dielectric structure is between the first portion and the second portion in the first direction (130 is between the first and second portions, as interpreted above, in the horizontal direction, as shown).
Regarding dependent claim 13, S1 further discloses in S1 FIG. 10 and associated text The IC device according to claim 8, wherein at least part of the dielectric structure is surrounded by an electrically conductive material (metal 150 is on either side of the structure in 130, therefore the dielectric structure is interpreted as being surrounded by electrically conductive material).
Regarding dependent claim 14, S1 further discloses in S1 FIG. 10 and associated text The IC device according to claim 8, wherein the semiconductor structure is electrically coupled to an electrically conductive layer (122 is electrically coupled to S/D contacts 154, which are interpreted as an electrically conductive layer), and the electrically conductive layer is closer to the first surface of the substrate than the second surface of the substrate (as shown, 154 is closer to the top surface of 102 than the bottom surface of 102).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over S1.
Regarding dependent claim 7, S1 discloses The IC device according to claim 1. S1 does not explicitly disclose the source contact or drain contact is electrically coupled to an electrically conductive layer, and the electrically conductive layer is closer to the first surface of the dielectric structure than the second surface of the dielectric structure.
However, Examiner takes official notice that conductive layers coupled to S/D contacts were well-known to those of ordinary skill in the art before the effective filing date of the invention. Such structures enable electrical connection of transistors within a larger device. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the IC device of S1 with an electrically conductive layer in contact with exposed portions of 154, which would result in a structure where the source contact or drain contact is electrically coupled to an electrically conductive layer, and the electrically conductive layer is closer to the first surface of the dielectric structure than the second surface of the dielectric structure (since exposed portions of 154 are coplanar with the top surface of 130, the electrically conductive layer would necessarily coincide with the top surface of 130, therefore being closer to it than to the bottom surface of 130) to enable electrical connection of transistors within a larger device.
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20200119004 A1, pertaining to alternative structures for diffusion breaks/fin trim isolations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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