DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species II, (claims 1-17) in the reply filed on 06/05/2026 is acknowledged.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/05/26.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features of claims 2-3, 16 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 defines “at least one of the nanoribbons of the first stack is vertically offset with respect to at least one of the nanoribbons of the second stack” is indefinite. As shown in Fig. 7 each one of the nanoribbons of the first stack is vertically offset with respect to each one of the nanoribbons of the second stack. Cancellation of the tern “at least” is suggested.
Claim 13 defines “wherein a thickness of one or more of the nanoribbons of the first stack is different from a thickness of one or more of the nanoribbons of the second stack” is indefinite. As shown in Fig. 7 each one of the nanoribbons of the first stack is different from a thickness of each one of the nanoribbons of the second stack. Appropriate correction is required.
Claims 2-3, 16 define projections and plane which are not shown or marked which make the claims ambiguous. Appropriate corrections/markings are required
Claims 2-12, 14-17 are also rejected being dependent on claims 1, 13.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miao et al (US 2019/0355723 A1).
Regarding claim 1: Miao teaches in Fig. 9 about an integrated circuit (IC) structure, comprising:
PNG
media_image1.png
590
780
media_image1.png
Greyscale
a support 10;
a first stack of nanoribbons (40) stacked above one another over the support, wherein portions of the nanoribbons of the first stack are channel regions of N-type transistors (nFET); and
a second stack of nanoribbons (42) stacked above one another over the support, wherein portions of the nanoribbons of the second stack are channel regions of P-type transistors (pFET),
wherein at least one of the nanoribbons of the first stack is vertically offset with respect to at least one of the nanoribbons of the second stack (as shown).
Regarding claim 11: Miao teaches in Fig. 9 about a first subfin 12 between the support and the first stack, wherein an uppermost portion of the first subfin includes a first semiconductor material; and
a second subfin 14 between the support and the second stack, wherein an uppermost portion of the second subfin includes a second semiconductor material,
wherein the first semiconductor material and the second semiconductor material have different material compositions [0019].
Regarding claim 12: Miao teaches in [0019] wherein the first semiconductor material includes silicon and the second semiconductor material includes germanium.
Claims 1-6, 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hickey et al (US 2021/0408285 A1).
Regarding claims 1, 13: Hickey teaches in Fig. 1B (c) about an integrated circuit (IC) structure, comprising:
PNG
media_image2.png
576
542
media_image2.png
Greyscale
a support 152;
a first stack of nanoribbons (left 156B) stacked above one another over the support, wherein portions of the nanoribbons of the first stack are channel regions of N-type transistors (NMOS); and
a second stack of nanoribbons (right 156B) stacked above one another over the support, wherein portions of the nanoribbons of the second stack are channel regions of P-type transistors (PMOS),
wherein at least one of the nanoribbons of the first stack is vertically offset with respect to at least one of the nanoribbons of the second stack (as marked).
Regarding claims 2, 16: Hickey teaches in Fig. 1B (c) wherein, when projected onto a plane that is substantially perpendicular to the support and substantially parallel to a longitudinal axis of the at least one of the nanoribbons of the first stack (in and out of the page direction), a projection of the at least one of the nanoribbons of the first stack is between projections of a pair of nearest-neighbor nanoribbons of the second stack.
Regarding claim 3: Hickey teaches in Fig. 1B (c) wherein a plane that is substantially parallel to the support and is along a middle of the at least one of the nanoribbons of the first stack is substantially in a middle between two adjacent nanoribbons of the nanoribbons of the second stack (as marked).
Regarding claims 4, 14: Hickey teaches in Fig. 1B (c) wherein a thickness of the at least one of the nanoribbons of the first stack is substantially equal to a distance between two adjacent nanoribbons of the nanoribbons of the second stack.
Regarding claims 5, 15: Hickey teaches in Fig. 1B (c) wherein a thickness of at least one of the nanoribbons of the second stack is substantially equal to a distance between two adjacent nanoribbons of the nanoribbons of the first stack.
Regarding claim 6: Hickey teaches in Fig. 1B (c) wherein a thickness of the at least one of the nanoribbons of the first stack is different from a thickness of the at least one of the nanoribbons of the second stack.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-10 are rejected under 35 U.S.C. 103 as being obvious over Hickey et al (US 2021/0408285 A1) in view of Li et al (CN 115172447 A).
Regarding claim 7: Hickey teaches wherein a thickness of each of the nanoribbons of the first stack is larger than a thickness of each of the nanoribbons of the second stack except wherein a thickness of each of the nanoribbons of the first stack is smaller than a thickness of each of the nanoribbons of the second stack.
Li teaches in Fig. 5 and in Fig. 25 the thickness of the channel material layer needed to prepare NMOS transistor is small, and the thickness of the channel material layer of the PMOS transistor used as the sacrificial layer is large, so as to satisfy the short channel effect of the NMOS transistor at the same time and also teaches the thickness of the first semiconductor material layer or the second semiconductor material layer may be 6 nm to 18 nm. The absolute value of the thickness difference between the first semiconductor material layer and the second semiconductor material layer can be 2 nm to 12 nm.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of application was filed to combine Li’ s teachings to Hickey’s semiconductor device to have the feature as claimed depending on device type and short channel effect consideration.
Regarding claim 8: Li teaches in Fig. 15 further comprising:
a first source region 28 for the N-type transistors of the first stack, the first source region extending vertically through the first stack;
a second source region 30 for the P-type transistors of the second stack, the second source region extending vertically through the second stack;
a first insulator structure 26 between the first source region and a gate electrode material 39 between two adjacent nanoribbons of the nanoribbons of the first stack; and
a second insulator structure 27 between the second source region and a gate electrode material 40 between two adjacent nanoribbons of the nanoribbons of the second stack,
wherein the first insulator structure is vertically offset with respect to the second insulator structure (as shown).
Regarding claim 9: Li teaches in Fig. 25 wherein a height of the first insulator structure 26 s substantially equal to a thickness of the at least one of the nanoribbons of the second stack 38.
Regarding claim 10: Li teaches in Fig. 25 wherein a height of the second insulator structure is substantially equal to a thickness of the at least one of the nanoribbons of the first stack.
Claim 17 is rejected under 35 U.S.C. 103 as being obvious over Hickey et al (US 2021/0408285 A1) in view of Chu et al (US PGPUB 20220320089 A1).
Regarding claim 17: Hickey does not explicitly talk about wherein a distance between the first stack and the second stack is less than about 500 nanometers.
Chu teaches in Fig. 6 a distance between the first stack and the second stack is 12 nm of left 219 + 12 nm of W2 + 12 nm of right 219 = 36nm
Therefore it would have been obvious to one of ordinary skill in the art, at the time of application was filed to combine Chu’ s teachings to Hickey’s semiconductor device to have the feature as claimed depending on submicron technology and scaling and width of isolation structure between the FET’s.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
Prosecution Insights