DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Final Action
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant's arguments filed 1/03/2025 have been fully considered but they are not persuasive.
Applicant argues:
For claim 1 the applicant argues that “Smedley cannot anticipate Claim 1 at least because Smedley fails to teach, disclose, or suggest, either expressly or inherently, each and every feature of Claim 1” and “There is no disclosure or suggestion in the description of Figure 5 of Smedley that the interpolator could receive any input based on the feedback signal. Indeed, feedback is not even mentioned in the description of Figure
5” and “Smedley fails to disclose or suggest the feature of claim 1 of "loop filter circuitry configured to receive an input signal based on the feedback signal and to output a digital loop filter output signal"
In response to the applicant’s argument:
The examiner respectfully disagrees because in the rejection under 35 USC § 102 as discussed was clearly provided explanations and point out all the evidences as found the prior art reference of Smedley. See Col. 5, lines 25-26 and Col. 5, lines which states “FIG. 9 is a simplified block diagram and schematic showing an integrated circuit design equivalent to the circuit of FIG. 5”. It is noted that Fig. 5 of Smedley disclosed Feedback line 80 (see Col. 8, lines 22-23), where two switches 40 and 42 which represent as an output stage circuit which drives the load 46 as shown in Fig. 5. Col. 8, lines 25-26, signals Vi 50 and feedback line 80 would be combined since signal Vi 50 and 82 are combined (emphasis added). As discussed above where feedback signal line 80 which combines with signal Vi 50 thus at least feedback loop form by elements 52, 56, 60 and 64), thus broadly, loop filter circuit including Interpolator 52 would receive input signal Vi 50 feedback signal 80 since signals Vi 50 and circuit 82 being combined. Fig. 5 of Smedley having analogous art arrangement, where A/D 58 disclosed between voltage source and divider 56 . Therefore, the examiner believes the evidences as found in reference of Smedley meeting claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8 & 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smedley (US 5,559,467 A, of record).
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Fig. 5 annotated for ease of reference
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Regarding claim 1, Smedley (Figs. 5 & 9) discloses an amplifier circuitry comprising:
output stage circuitry (switches 40 and 42) configured to modulate a power supply voltage (Supply voltage Vs in Figs. 5 & 9), based on a drive signal (PWM signal from PWM 64) received at an input of the output stage circuitry, to generate an amplifier output signal (Vo);
a feedback path (Fig. 9 and annotated Fig. 5 and Col. 8, lines 22-28, “Audio feedbacks are provided on feedback line 80 to the noise and ripple shaping chip 82 which takes as its other inputs the digital input signal 50 and VS, the unregulated power source voltage 82. The signals on lines 50 and 82 are then combined within noise and ripple shaping chip 82 in the manner as described in connection with FIG. 5 to provide a PWM output signal 86 provided as a control signal to complementary switches 40 and 42 to drive the load) coupled to an output (Vo) of the output stage circuitry and configured to generate a feedback signal based on the amplifier output signal;
loop filter circuitry (e.g., interpolator 52, Col. 6, lines 25-27, “The digital audio input, Vi, is interpolated by interpolator 52 to create an over-sampled digital signal on output 54” and also see Col. 4, lines 17-21, an interpolator for reducing distortion) configured to receive an input signal based on the feedback signal and to output a digital loop filter output signal (an over-sampled digital signal on output 54);
divider circuitry (Col. 6, line 28-29, divider 56) configured to divide the digital loop filter output signal by the power supply voltage to generate a divided digital output signal; and
encoder circuitry (e.g., Pulse Width Modulator 64) configured to generate the drive signal based on the divided digital output signal.
Regarding claim 2, Smedley (Figs. 5 & 9) discloses wherein the output stage circuitry comprises Class D output stage circuitry (Col. 4, lines 34-41, switching amplifier where output stage includes two switches 40 and 42 which operating in class D, it is noted that the output stage drives the load where the load is speaker, see Col. 5, last paragraph) .
Regarding claim 8, Smedley (Figs. 5 & 9) discloses wherein the encoder circuitry comprises pulse width modulation (PWM) encoder circuitry (e.g., pulse width modulator 64, see Col. 6, lines 35-39).
Regarding claim 14, Smedley (Figs. 5 & 9) discloses an integrated circuit (Col. 5, line 38-40) comprising amplifier circuitry according to claim 1.
Regarding claim 15, Smedley discloses host device (e.g., an audio compact disk player, Col. 5, last paragraph and Col. 6, first paragraph) comprising amplifier circuitry according to claim 1; and (Claim 16) The host device according to claim 15, wherein the host device comprises a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player (an audio compact disk player, Col. 5, last paragraph and Col. 6, first paragraph), a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device.
Allowable Subject Matter
Claims 3-7 & 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREA J LINDGREN BALTZELL can be reached at (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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