DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Application and preliminary amendment filed on 3/10/2023. Claims 1-16,19-20,29,34 are pending, wherein claims 17-18,21-28,30-33,35-56 have been canceled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-12,15-16,19-20,29,34 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by C et al. (US Patent Application Publication No. 2024/0078368 A1).
The applied reference has a common assignee and inventors with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As per claims 1,15, 29, Fig. 4 illustrates the elements of the claims, comprising:
access circuit design data to be optimized by an electronic design automation (EDA) tool as part of a circuit design process for an integrated circuit (i.e., step 410);
extract features from the circuit design data (step 420);
apply a machine learning model to the features to estimate an output of the EDA tool, the estimated output determined without execution of the EDA tool (steps 430-460); and
provide results of the estimated output (step 470); (see also paragraphs [0064]-[0074]);
wherein the programmable circuitry to at least one of instantiate or execute the machine readable instructions are described in paragraph [0020]; the machine readable instructions are described in paragraphs [0037]-[0039], abstract; the interface are described in paragraphs [0020], [0097]; wherein the feature extraction circuitry, model generation circuitry, results circuitry, model application circuitry and model optimization circuitry are further illustrated in Fig. 2.
As per claims 2-4,16, the circuit design data is an input for a portion of a construction phase of the circuit design process, which includes at least one of logic synthesis stage or physical synthesis stage, placement stage, clock tree synthesis or routing stage are illustrated in Fig. 1, for which the method/system/apparatus/non-transitory machine readable medium of claims 1, 15, 29, upon which the respective claims depend, are being applied.
As per claims 5,19, the circuit design data is an input for a portion of a sign-off phase of the circuit design process is also described in paragraph [0032].
As per claims 6-8,20,34, the circuit design data includes a gate-level description of an integrated circuit (see paragraph [0027], i.e., Boolean logic gates), which specifies cells in in the integrated circuit and timing paths associated with the cells, wherein the features corresponds to at least one of a functionality (abstract), fain-in count, a fan-out count (see paragraph [0064], a slack, a path phase, a path depth (see paragraph [0064], [0079]), a sequence of cells in one of the timing paths (paragraphs [0069], [0077], a slack (paragraph [0028], i.e., delay) a start clock, an end clock (paragraphs [0028], [0058]-[0059] i.e., clock network which contains start clock, end clock as known in the art).
As per claim 9-10, the results include an estimate of a path depth for ones of the timing paths (see paragraph [0064],), an estimate of a sequence of the cells in ones of the timing paths (see paragraphs [0077], [0046]-[0048]
As per claim 11, the programmable circuitry is to generate the machine learning model (see paragraph [0038]).
As per claim 12, the programmable circuitry is to generate the machine learning model based on supervised training of the machine learning model using unoptimized training data and optimized training data, the unoptimized training data not having been processed through the EDA tool to converge at a solution that meets design specifications and quality checks for the integrated circuit, the optimized training data having been processed through the EDA tool to converge at the solution that meets the design specifications and quality checks for the integrated circuit (see paragraphs [0070]-[0075], i.e., supervised machine learning performed in iterative loop that includes both unoptimized training data and optimized training in order to satisfy all designing constraints).
Claim(s) 1-12,15-16,19-20,29,34 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nath et al. (US Patent No.12,124782 B1).
As per claims 1,15, 29, Fig. 1 illustrates the elements of the claims, comprising:
access circuit design data to be optimized by an electronic design automation (EDA) tool as part of a circuit design process for an integrated circuit (i.e. design data such as routed gate-level netlist 110, timing estimates 130, GBA data 132, PBA data 160 are accessed);
extract features from the circuit design data (performed at block 134—see col. 4, lines 21-28);
apply a machine learning model to the features to estimate an output of the EDA tool, the estimated output determined without execution of the EDA tool (performed in blocks 134-140; (see also col. 3, line 55 to col. 4, line 29); and
provide results of the estimated output (block 190);
wherein the programmable circuitry to at least one of instantiate or execute the machine readable containing instructions, interface are illustrated in Fig. 8 and described in col. 14, lines 24-67, for which the various portions are implemented as the feature extraction circuitry/block, model generation circuitry/block, results circuitry/block, model application circuitry/block and model optimization circuitry/block as illustrated in Fig. 1.
As per claims 2-4,16, the circuit design data is an input for a portion of a construction phase of the circuit design process, which includes at least one of logic synthesis stage or physical synthesis stage, placement stage, clock tree synthesis or routing stage are described in col. 12, line 61 to col. 14, line 23 (see also Fig. 7), for which the method/system/apparatus/non-transitory machine readable medium of claims 1, 15, 29, upon which the respective claims depend, are being applied.
As per claims 5,19, the circuit design data is an input for a portion of a sign-off phase of the circuit design process is also described in col. 9, line 27 to col. 10, line 43.
As per claims 6-8,20,34, the circuit design data includes a gate-level description of an integrated circuit (Fig. 1, block 110), which specifies cells in in the integrated circuit and timing paths associated with the cells (col, 2, line 54 to col. 3, line 44), wherein the features corresponds to at least one of a functionality, fain-in count and a fan-out count (i.e., count of pin nodes), a slack, a path depth, a sequence of cells in one of the timing paths are described in col. 5, line 8 to col. 6, line 58 and Table 1, col. 4, lines 45-55.
As per claim 9-10, the results include an estimate of a path depth for ones of the timing paths (see col. 6, line 66 to col. 7, line 6), an estimate of a sequence of the cells in ones of the timing paths (see col. 5, lines 20-67).
As per claim 11, the programmable circuitry is to generate the machine learning model (Fig. 1, block 140 for which the programmable circuitry described in col. 14, lines 24-67 could implement to generate this ML model).
As per claim 12, the programmable circuitry is to generate the machine learning model based on supervised training of the machine learning model using unoptimized training data and optimized training data, the unoptimized training data not having been processed through the EDA tool to converge at a solution that meets design specifications and quality checks for the integrated circuit, the optimized training data having been processed through the EDA tool to converge at the solution that meets the design specifications and quality checks for the integrated circuit (see col. 5, line 9 to col. , which involves supervised training model—col. 6, lines 46-58; performed in iterative loop 150 of Fig. 1 which includes both optimized and unoptimized training data).
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if claim 13 is rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As per claims 13-14, the claims further recite a combination of inventive steps/operations of the extracting sequences of cells in timing paths defined for the integrated circuit; classify the sequences of the cells using an unsupervised machine learning algorithm; and filter the sequences of the cells based on the classification, the unoptimized training data based on the filtered sequences, as claimed, which the prior arts made of record failed to teach or suggest as claimed. In particular, although C et al. disclose that the learning algorithms could be unsupervised machine learning algorithms (see paragraph [0070]) and Rimestad et al. teach machine learning involving feature quantification, feature clustering and image classification, involving the use of unsupervised learning algorithms (see paragraphs [0163], [0184], [201], [214]), neither C et al. nor Rimestad et al., alone or in combination with the prior arts made of record teach or suggest the combinations of inventive steps/operations as claimed. Furthermore, under the 2019 Patent Eligibility Guideline, the claims are directed to patent eligible subject matter because (1) under Step 1, the claims are directed to a process, article of manufacture and machine, respectively; (2) under Step 2A, Prong One, the claims are not directed to mathematical concepts comprising mathematical relationships, mathematical formulas or equations, and mathematical calculations since no expressed equation or formula is recited in the claims; nor are the claims directed to a mental process since one of ordinary skilled in the art at the time of the filing of the invention, would NOT reasonably be able to perform the method mentally since the calculations would involve large amount of data associated with the electronic design, as normally found in the art of computer-aided design and analysis of circuits; nor are the claims directed to certain methods of organizing human activity.
Conclusion
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/PHALLAKA KIK/Primary Examiner, Art Unit 2851 March 6, 2026