DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment
Acknowledgment is made of applicant's Amendment, filed 02-04-2026. The changes and remarks disclosed therein have been considered.
Claim(s) 1-3 has/have been amended, claim(s) 5-10 has/have been added by amendment, claim(s) 1-10 remain(s) pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gogl, US 6982902 B2, in view of Kyung, US 20160260477 A1.
As to claim 1, Gogl discloses a memory device (see Gogl Fig 4B), comprising:
a plurality of word lines (see Gogl Fig 4B Ref 232);
and a plurality of memory units (see the annotated image of Gogl Fig 4B below), each of the memory units comprising:
a plurality of memory cell groups (see the annotated image of Gogl Fig 4B below), each of the memory cell groups comprising a plurality of memory cells (see Gogl Fig 4B Ref R_MTJ);
at least one bit line (see Gogl Fig 4B Ref 222);
wherein
in each of the memory units, at least one of the plurality of word lines is coupled to at most one of the memory cells (see Gogl Fig 4B Refs K-1 to K+14).
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Gogl does not appear to explicitly disclose
a column word line;
a plurality of column switches, each of the column switches having a control terminal coupled to the column word line, a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit, wherein
the control terminals of the plurality of column switches are coupled to the same column word line.
Kyung discloses
a column word line (see Kyung Fig 2 Ref LY);
a plurality of column switches (see Kyung Fig 2 Ref 122), each of the column switches having a control terminal coupled to the column word line (see Kyung Fig 2 Ref 122), a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line (see Kyung Fig 2 Ref 122 and the annotated image of Gogl Fig 4B above and Kyung Fig 2 below; Coupled does not imply directly coupled.), wherein
the control terminals of the plurality of column switches are coupled to the same column word line (see Kyung Fig 2 Ref LY).
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It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a semiconductor device, as disclosed by Gogl, may have a particular arrangement of switches and lines to access memory cells, as disclosed by Kyung. The inventions are well known variants of access arrangements for memory cell groups, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Kyung’s attempt to shorten read cycles (see Kyung Para [0068]).
As to claim 2, Gogl and Kyung disclose the memory device of claim 1, wherein
the plurality of column switches are transistors (see Kyung Fig 2 Ref 122).
As to claim 3, Gogl discloses a memory device (see Gogl Fig 4B), comprising:
a plurality of word lines (see Gogl Fig 4B Ref 232); and
a plurality of memory units (see the annotated image of Gogl Fig 4B above), each of the memory units comprising:
a plurality of memory cell groups (see the annotated image of Gogl Fig 4B above), each of the memory cell groups comprising a plurality of memory cells (see Gogl Fig 4B Ref R_MTJ);
at least one bit line (see Gogl Fig 4B Ref 222); wherein
in each of the memory units, at least one of the plurality of word lines is coupled to at most one memory cells (see Gogl Fig 4B Refs K-1 to K+14).
Gogl does not appear to explicitly disclose
a column word line; and
a plurality of column switches, each of the column switches having a control terminal coupled to the column word line, a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line, wherein
the control terminals of at least two of the column switches are coupled to the same column word line.
Kyung discloses
a column word line (see Kyung Fig 2 Ref LY); and
a plurality of column switches (see Kyung Fig 2 Ref 122), each of the column switches having a control terminal coupled to the column word line (see Kyung Fig 2 Ref 122), a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line (see Kyung Fig 2 Ref 122 and the annotated image of Gogl Fig 4B above and Kyung Fig 2 above; Coupled does not imply directly coupled.), wherein
the control terminals of at least two of the column switches are coupled to the same column word line (see Kyung Fig 2 Ref LY)
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a semiconductor device, as disclosed by Gogl, may have a particular arrangement of switches and lines to access memory cells, as disclosed by Kyung. The inventions are well known variants of access arrangements for memory cell groups, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Kyung’s attempt to shorten read cycles (see Kyung Para [0068]).
As to claim 4, Gogl and Kyung disclose the memory device of claim 3, wherein
the plurality of column switches are transistors (see Kyung Fig 2 Ref 122).
As to claim 5, Gogl and Kyung disclose the memory device of claim 1, wherein
the memory devices further comprises a plurality of row word lines (see Gogl Fig 4B Ref 210), and each of the memory units further comprises:
a plurality of row switches (see Gogl Fig 4B Ref 208), each of the row switches having a control terminal coupled to the corresponding row word line (see Gogl Fig 4B Ref 208); wherein
each of the column switches and the corresponding row switch are coupled in series between the at least one bit line and the plurality of memory cells of the corresponding memory cell group (see Kyung Fig 2 Ref 122 and the annotated image of Gogl Fig 4B above and Kyung Fig 2 above).
As to claim 6, Gogl and Kyung disclose the memory device of claim 5, wherein
the plurality of column switches (see Kyung Fig 2 Ref 122) and the plurality of row switches are transistors (see Gogl Fig 4B Ref 208).
As to claim 7, Gogl and Kyung disclose the memory device of claim 3.
Claim 7 recites substantially the same limitations as claim 5.
All the limitations of claim 7 have already been disclosed by Gogl and Kyung in claim 5 above.
As to claim 8, Gogl and Kyung disclose the memory device of claim 7.
Claim 8 recites substantially the same limitations as claim 6.
All the limitations of claim 8 have already been disclosed by Gogl and Kyung in claim 6 above.
As to claim 9, Gogl and Kyung disclose a memory device (see Gogl Fig 4B), comprising:
a plurality of word lines (see Gogl Fig 4B Ref 232); and
a plurality of memory units (see the annotated image of Gogl Fig 4B above), each of the memory units comprising:
a plurality of memory cell groups (see the annotated image of Gogl Fig 4B above), each of the memory cell groups respectively controlled by the plurality of word lines and comprising a plurality of memory cells (see Gogl Fig 4B Ref R_MTJ);
at least one bit line (see Gogl Fig 4B Ref 222);
at least one column word line (see Kyung Fig 2 Ref LY); and a plurality of column switches (see Kyung Fig 2 Ref 122), each of the column switches having a control terminal coupled to the column word line (see Kyung Fig 2 Ref 122), a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line (see Kyung Fig 2 Ref 122 and the annotated image of Gogl Fig 4B above and Kyung Fig 2 below; Coupled does not imply directly coupled.), wherein
the control terminals of at least two of the column switches are coupled to the same column word line (see Kyung Fig 2 Ref LY).
As to claim 10, Gogl and Kyung disclose the memory device of claim 9.
Claim 10 recites substantially the same limitations as claim 5.
All the limitations of claim 10 have already been disclosed by Gogl and Kyung in claim 5 above.
Response to Arguments
Applicant's arguments filed 02/04/2026 have been fully considered but they are not persuasive.
The amended language does not appear to overcome the prior art of record.
Conclusion
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 02/21/2026