DETAILED ACTION
Election/Restrictions
A restriction requirement was mailed on 8/11/25.
Applicant’s election without traverse of Group I in the reply filed on 10/6/25 is acknowledged. Claims 18-20 are withdrawn.
Claim Objections
Claims 1 and 9 are objected to because “second length” in the limitation “wherein the power via has second length” lacks proper antecedent basis and should be changed to “a second length”.
Claims 3, 7, 11, and 15 are objected to because “a gate direction” lacks proper antecedent basis due to “a gate direction” in claims 1 and 9; in claims 3, 7, 11, and 15 it should be changed to “the gate direction”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0369222 A1 (“Engel”).
Engel teaches, for example:
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Engel teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A microelectronic structure (see e.g. Fig. 4) comprising:
a plurality of nanosheet transistors 204,
wherein each of the plurality of nanosheet transistors includes an active gate 210 located around a plurality of active channel layers 208,
wherein each of the plurality of nanosheet transistors includes a source/drain region 214 having a first length (e.g. length from left to right in Fig. 4),
wherein the first length is measured perpendicular to a gate direction (e.g. direction “into the page” as shown in Fig. 4) of the plurality of nanosheet transistors; and
a power via (e.g. comprising “backside metal structure 410”, see para 38, and “conductive feedthrough structure” 410, see para 38; both are for “backside power delivery”, see e.g. para 5, 6, 32, 38) located between a first dummy device and a second dummy device (it is reasonable to interpret the parts of 202B, 214, and 216 in “non-active region 222” as parts of “dummy devices”; the parts to the left of 3rd-to-left 224 in Fig. 2A can be interpreted as “first dummy device” and the parts to the right of 3rd-to-left 224 in Fig. 2A can be interpreted as a “second dummy device”, and the power via 410/412 separates these in Fig. 4),
wherein the power via has a second length (e.g. the length of 410 from left-to-right in Fig. 4; or the length of 412 from left-to-right in Fig. 4), wherein the second length is measured perpendicular to the gate direction of the plurality of nanosheet transistors (it is measured from left-to-right in Fig. 4),
Engel does not explicitly teach wherein the second length is larger than the first length, because no specific lengths are disclosed in the text, and the drawings are not said to be drawn to scale. However, Engel teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention wherein the second length is larger than the first length because in Fig. 4 the drawing shows 410 to have a larger length from left-to-right than 214. While the drawing is not necessarily to scale, the portion 412 is formed through a source/drain region 214 (see evolution from Fig. 2A to Fig. 4) and the portion 410 is clearly wider than the removed portion where 214 was. It is reasonable to interpret that all 214s should be the same width, as they are drawn to the same width.
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Furthermore, applicant has not disclosed that the claimed relationship between the first and second lengths is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical. It has been found that mere changes in the size of an object, lacking any convincing proof of criticality or unobviousness thereof, is not sufficient for patentability. See e.g. MPEP 2144.04; in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); in re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984);
To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See e.g. MPEP 716.02(b); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
2. The microelectronic structure of claim 1, wherein the power via includes a top section (e.g. 410), a middle section (e.g. portion of 412 directly within 202B), and a bottom section (e.g. portion of 412 above the surface of 202B in Fig. 4) (regarding “top” and “bottom”, one may rotate Fig.4 by 180 degrees).
3. The microelectronic structure of claim 2, wherein the top section has a third length (e.g. width of 410), wherein the third length is measured perpendicular to a gate direction of the plurality of nanosheet transistors, wherein the third length is larger than the second length (410 is wider than 412).
4. The microelectronic structure of claim 3, wherein the power via has a shape of a bolt (it is wider on one end and has a relatively thin “shaft”, the same shape as a bolt has; this is the same general shape that Applicant’s power via has, and which is described as a “bolt”).
5. The microelectronic structure of claim 4, wherein a length of the middle section and the bottom section is the second length (412 has the same length from left-to-right throughout).
9. A microelectronic structure (see e.g. Fig. 4) comprising:
a plurality of nanosheet transistors 204,
wherein each of the plurality of nanosheet transistors includes an active gate 210 located around a plurality of active channel layers 208,
wherein each of the plurality of nanosheet transistors includes a source/drain region 214 having a first length (e.g. length from left to right in Fig. 4),
wherein the first length is measured perpendicular to a gate direction (e.g. direction “into the page” as shown in Fig. 4) of the plurality of nanosheet transistors; and
a power via (e.g. comprising “backside metal structure 410”, see para 38, and “conductive feedthrough structure” 410, see para 38; both are for “backside power delivery”, see e.g. para 5, 6, 32, 38) located between a first dummy device and a second dummy device (it is reasonable to interpret the parts of 202B, 214, and 216 in “non-active region 222” as parts of “dummy devices”; the parts to the left of 3rd-to-left 224 in Fig. 2A can be interpreted as “first dummy device” and the parts to the right of 3rd-to-left 224 in Fig. 2A can be interpreted as a “second dummy device”, and the power via 410/412 separates these in Fig. 4),
wherein the power via has a second length (e.g. the length of 410 from left-to-right in Fig. 4; or the length of 412 from left-to-right in Fig. 4),
wherein the second length is measured perpendicular to the gate direction of the plurality of nanosheet transistors (it is measured from left-to-right in Fig. 4),
wherein the first dummy device is located flush against a first side of the power via and the second dummy device is located flush against a second side of the power via (see Fig. 4, wherein 412 is flush with 202B on both of its left and right sides; as described above, these mark the outer boundaries of the first and second dummy devices).
Engel does not explicitly teach wherein the second length is larger than the first length, because no specific lengths are disclosed in the text, and the drawings are not said to be drawn to scale. However, Engel teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention wherein the second length is larger than the first length because in Fig. 4 the drawing shows 410 to have a larger length from left-to-right than 214. While the drawing is not necessarily to scale, the portion 412 is formed through a source/drain region 214 (see evolution from Fig. 2A to Fig. 4) and the portion 410 is clearly wider than the removed portion where 214 was. It is reasonable to interpret that all 214s should be the same width, as they are drawn to the same width.
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Furthermore, applicant has not disclosed that the claimed relationship between the first and second lengths is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical. It has been found that mere changes in the size of an object, lacking any convincing proof of criticality or unobviousness thereof, is not sufficient for patentability. See e.g. MPEP 2144.04; in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); in re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984);
To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See e.g. MPEP 716.02(b); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
10. The microelectronic structure of claim 9, wherein the power via includes a top section (e.g. 410), a middle section (e.g. portion of 412 directly within 202B), and a bottom section (e.g. portion of 412 above the surface of 202B in Fig. 4) (regarding “top” and “bottom”, one may rotate Fig.4 by 180 degrees).
11. The microelectronic structure of claim 10, wherein the top section has a third length (e.g. width of 410), wherein the third length is measured perpendicular to a gate direction of the plurality of nanosheet transistors, wherein the third length is larger than the second length (410 is wider than 412).
12. The microelectronic structure of claim 11, wherein the power via has a shape of a bolt (it is wider on one end and has a relatively thin “shaft”, the same shape as a bolt has; this is the same general shape that Applicant’s power via has, and which is described as a “bolt”).
13. The microelectronic structure of claim 12, wherein a length of the middle section and the bottom section is the second length (412 has the same length from left-to-right throughout).
Allowable Subject Matter
Claim(s) 6-8 and 15-17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 6, 8, 14, 16, or 17, including:
6. The microelectronic structure of claim 5, further comprising: a spacer located adjacent to sidewalls of the bottom section of the power via, wherein the spacer extends along a height of the bottom section; and a metal line connected to a bottom surface of the bottom section of the power via.
8. The microelectronic structure of claim 1, wherein the power via has a first width as measured parallel to the gate direction of the plurality of nanosheet transistors, wherein the each of the plurality of transistors has a second width as measured parallel to the gate direction of the plurality of nanosheet transistors, wherein the first width is larger than the second width.
14. The microelectronic structure of claim 13, further comprising: a spacer located adjacent to sidewalls of the bottom section of the power via, wherein the spacer extends along a height of the bottom section; and a metal line connected to a bottom surface of the bottom section of the power via.
16. The microelectronic structure of claim 9, wherein the power via has a first width as measured parallel to the gate direction of the plurality of nanosheet transistors, wherein the each of the plurality of transistors has a second width as measured parallel to the gate direction of the plurality of nanosheet transistors, wherein the first width is larger than the second width.
17. The microelectronic structure of claim 9, wherein the power via is a shared power via that extends across at least two nanosheet transistors, wherein the shared power via is located additionally between a third dummy device and a fourth dummy device.
The other claims each depend from one of these claims, and each would be allowable for the same reasons as the claim from which it depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
US 2023/0131382 A1 (“Ding”) teaches dummy region DMR (cover figure) with a contact structure TCT therein (see also e.g. Fig. 2E).
US 2020/0373402 A1 (“Yang”) teaches a dummy gate can go between nanosheet transistors in region 105 (see e.g. cover figure and Figs. 11-12).
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896