DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The deferral of examination under 37 CFR 1.103(d) of the present Application for a period of 36 months from the earliest filing date 03/13/2023 is now expired.
This is a Second NON-FINAL OFFICE ACTION in response to the present Application filed 03/13/2023. A First NON-FINAL OFFICE ACTION was mailed 07/30/2024 inadvertently during the suspension period as a result of a USPTO docketing error.
Claims 1-20 are pending in the Application, of which Claims 1, 12 and 17 are independent.
Claim Objections
Claims 1-11 are objected to because of the following informalities:
Claim 1, change “structural flaw” to “structural communication flaw” as to comply with proper antecedent basis.
Claim 3, change “generating a recommendation” to “generating a compensation recommendation” for consistency. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent Claims 1, 12 and 17, recite the limitation “generating…a compensation recommendation” which renders the Claims indefinite. The use of the word “recommendation” implies subjective opinion with no support in the specification. Normally, a system is configured to perform compensation or not based on test results. The system or method does not recommend.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “wander” in claims 1, 12 and 17, as best understood is used by the claim to mean “a voltage level out of tolerance or there is a drift in the signal or there is jitter in the signal” while the accepted meaning is “to move about without a fixed course, aim, or goal” according to the dictionary. The term is indefinite because the specification does not clearly redefine the term.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 12-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eguchi et al. (Pub. No. US 20130326285) Pub. Date: 2013-12-05.
Regarding independent Claims 1, 12 and 17, Eguchi discloses stress-based techniques for accelerating and detecting an imminent read failure in a non-volatile memory array, comprising:
receiving, via a processor, test results that indicate baseline interface voltage level that is from a transient data transmission and is measured at the computer memory;
[0030] With reference to FIG. 5, a memory system 500 is illustrated that includes a non-volatile memory (NVM) array 502, an ECC circuit 504 (in a read path of the NVM array 502), a margin read circuit 506 (including a threshold voltage adjuster 516), an address generator 508, a stress circuit 510, and a compare circuit 520 (including an array integrity (AI) check circuit 512 and a multiple input signature register (MISR) 514).
[0031] The compare circuit 520 then compares subsequent signatures of the sequence of read data (when read at a later point in time) to an initial signature to identify read failures. The ECC circuit 504 identifies whether a read needed a correction to pass (as well as identifying whether a read could not be corrected due to too many failures in the ECC word checkbase). The margin read circuit 506 is used to perform a read at one or more margin read verify voltage levels.
in response to detecting, via the processor, that the test results indicate a baseline wander for the baseline interface voltage level of the computer memory, generating via the processor and based on the baseline wander an identification of an associated structural communication flaw of the computer memory;
[0037] Next, in decision block 708, the process 700 determines whether the AI check passed without ECC correction. If the AI check did not pass in block 708 without ECC correction, control transfers to decision block 712, where the process 700 determines whether the part is ECC correctable (as, for example, indicated by an ECC flag). If the NVM array 502 is not ECC correctable in block 712, control transfers to block 720 where a fail status is indicated.
a compensation recommendation for compensating for the structural flaw
[0032] The threshold voltage level adjuster 516 (which is coupled to a wordline driver) changes a wordline/gate voltage (above or below a normal read verify voltage level) of a field-effect transistor (FET) of a cell such that a read can be performed at a desired margin read verify voltage level.
[0038] If the NVM array 502 is ECC correctable in block 712, control transfers to block 714 where a read level is decreased to a low margin threshold voltage to check expected erased bits and another AI check is performed. In block 714, any uncorrectable reads are captured. Next, in block 716, a read level is increased to a high margin threshold voltage to check expected programmed bits and yet another AI check is performed. In block 716, any uncorrectable reads are captured.
transmitting, via the processor, the compensation recommendation for presentation of the compensation recommendation. [0038] Then, in decision block 718, the process 700 determines whether any uncorrectable reads were captured in blocks 714 and 716. If no uncorrectable reads were captured in blocks 714 and 716, control transfers from block 718 to block 710. If uncorrectable reads were captured in blocks 714 or 716, control transfers from block 718 to block 720. Following blocks 710 and 720, control transfers to block 722 (where the diagnostic mode is exited) and then to block 724 (where control returns to a calling process and the process 700 is terminated).
Regarding Claims Eguchi discloses 2-4, 13-15, 18-20, wherein the associated structural communication flaw comprises a number of failing lanes in the computer memory. [0031] With reference to FIG. 5, the compare circuit 520 then compares subsequent signatures of the sequence of read data (when read at a later point in time) to an initial signature to identify read failures. The ECC circuit 504 identifies whether a read needed a correction to pass (as well as identifying whether a read could not be corrected due to too many failures “flaw” in the ECC word checkbase). The margin read circuit 506 is used to perform a read at one or more margin read verify voltage levels.
[0034] FIG. 6 shows an example of bulk read stress condition on a relevant portion of the NVM array 502 according to one embodiment. According to one embodiment, all even rows (gates) of the NVM array 502 are biased with 6V while all odd rows (gates) are grounded and all even columns (drains) of the NVM array 502 are biased with 0.5V while all odd columns (drains) of the NVM array 502 are grounded. This bias condition is maintained for a predetermined duration, e.g., about 3 to 6 minutes, to stress all the even rows and columns, where in this case corresponding to lanes as Claimed.
If the NVM array 502 is not ECC correctable in block 712, control transfers to block 720 where a fail status “flaw” is indicated.
Regarding Claims 5, 6, 7, 16, Eguchi discloses operate the computer memory in a degraded mode, and to reroute a defective lane of the computer memory to another lane of the computer memory. [0037 If the AI check did not pass in block 708 without ECC correction, control transfers to decision block 712, where the process 700 determines whether the part is ECC correctable (as, for example, indicated by an ECC flag). If the NVM array 502 is not ECC correctable in block 712, control transfers to block 720 where a fail status “flaw” is indicated. [0038] If uncorrectable reads were captured in blocks 714 or 716, control transfers from block 718 to block 720. Following blocks 710 and 720, control transfers to block 722 (where the diagnostic mode is exited) and then to block 724 (where control returns to a calling process and the process 700 is terminated).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Eguchi et al. (Pub. No. US 20130326285) in view of Froelich et al. (Pub. No. US 20220163587) Pub. Date: 2022-05-26.
Regarding Claims 8-11 fails to explicitly disclose inputting the test results into a machine learning model and receiving output from the machine learning model.
However, in analogous art, Froelich discloses para. [0063] Embodiments of the invention greatly expand the analysis of such test results as described with FIG. 9 to a system that can generate and store historical records of previous margin tests of particular components. Then, those historical records can be analyzed to detect patterns of failures and successes. This failure rate data may be added much later than the original data, for example months or years later. Artificial analysis, machine learning, or other methods may be used to study the dataset and compare it to the failure rate data, or other data gathered about the devices. With enough training, analysis results may be used to generate predictions indicators or early signals of potential problems that may arise with devices in the future.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use a machine learning in the device of Eguchi as taught by Froelich as with enough training, analysis results may be used to generate predictions indicators or early signals of potential problems that may arise with devices in the future.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
US 20100169729 DATTA; SHAMANNA M. et al. [0024] Logic to compensate for the marginal condition performs an action at 306. In some embodiments, compensating for the marginal condition includes detecting hard errors and relocating information to a known good memory location. In some embodiments, the compensating logic uses a memory map to reference the new locations for the relocated data.
US 20220163588 Froelich; Daniel S. et al. See, Abstract. A margin testing device includes at least one interface structured to connect to a device under test (DUT) one or more controllers structured to create a set of test signals based on a sequence of pseudo random data and one or more pre-defined parameters, and an output structured to send the set of test signals to the DUT.
US 20030169622 Ooishi, Tsukasa et al. [0269] In addition, a memory cell with a margin failure is detected, and a sense current (reference current) is adjusted according to a result of the detection so as to compensate for the margin failure. Margin compensation can be performed correctly only for a memory cell with a margin failure.
US 20250201287 Lee; Choongeui [0060] The margin collector 161 may generate three or more sampling DQS signals in the left capture path (first capture path circuit 120a) and the right capture path (the second capture path circuit 120b) during a read DMA operation, and may capture a DQ signal using the generated sampling DQS signals. The margin collector 161 may compare read data normally captured in the main path circuit 110a and sampling data captured by each sampling DQS signal, may determine whether there is an error as a result of the comparison.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached on (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: April 22, 2026
Non-Final Rejection 20260422
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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