DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nitta (US Publication 20240028861).
Regarding claim 1, Nitta teaches a chip-interconnect arrangement, comprising: a substrate having a cavity (Fig. 2, 6 including 2 - more clearly because 6 includes many elements, the substrate for clarity is specifically 2 and A2, para 7-8); a chip having at least one chip contact (Fig. 2, 5) and one chip contact surface (Fig. 3, 32), the chip being arranged in the cavity (Fig. 2, 5 in cavity of 6 specifically layer A2); an interconnect having an interconnect surface (Fig. 3, 31-36), the interconnect being applied on a surface of the substrate (Fig. 4, 31, 33, 35 on 2 and A2); and an electrically conductive adhesion medium (para 48), which electrically connects the at least one chip contact to the interconnect (para 48), wherein the adhesion medium comprises a planar surface (Fig. 4, planar surface at interface of 5 and 31).
Regarding claim 2, Nitta teaches the limitations of claim 1 upon which claim 2 depends. Nitta teaches wherein when the chip-interconnect arrangement bears on a horizontal surface with a chip facing away from the surface, and the planar surface of the adhesion medium is substantially parallel to the horizontal surface (Fig. 4, planar surface along x axis, 5 facing away from 2/A2, substantially parallel to x axis).
Regarding claim 3, Nitta teaches the limitations of claim 1 upon which claim 3 depends. Nitta teaches wherein the chip contact surface, the interconnect surface and a surface of the adhesion medium are coplanar with respect to one another or the adhesion medium is coplanar with respect to that surface out of the chip contact surface and the interconnect surface which is further away from a principal plane of the substrate (Fig. 4, 5 contact surface on adhesion medium with interconnects 31, 33, and 35 coplanar along x axis).
Regarding claim 5, Nitta teaches the limitations of claim 1 upon which claim 5 depends. Nitta teaches wherein the interconnect has an antenna (Fig. 3, 3 including 31, 33-36, para 38-39).
Regarding claim 6, Nitta teaches the limitations of claim 1 upon which claim 6 depends. Nitta teaches wherein the adhesion medium is coplanar with the interconnect surface (Fig. 4, coplanar intersection of 5 and 3).
Regarding claim 7, Nitta teaches the limitations of claim 1 upon which claim 7 depends. Nitta teaches wherein the chip comprises a plurality of edges which form a polygon, and wherein an individual chip contact of the at least one chip contact extends along at least two edges (para 48, Fig. 4, chip 5 4-sided polygon).
Regarding claim 8, Nitta teaches the limitations of claim 7 upon which claim 8 depends. Nitta teaches wherein the adhesion medium contacts the individual chip contact across at least one of the two edges (para 48, Fig. 4, chip 5 4-sided polygon).
Regarding claim 9, Nitta teaches the limitations of claim 1 upon which claim 9 depends. Nitta teaches wherein the at least one chip contact comprises an L-shape (Fig. 4, chip 5 where the chip contacts the interconnect and forms L shape).
Regarding claim 10, Nitta teaches the limitations of claim 1 upon which claim 10 depends. Nitta teaches wherein the chip-interconnect arrangement comprises a thickness of a maximum of 80 micro meters (para 35, 50 micro meters).
Regarding claim 11, Nitta teaches the limitations of claim 1 upon which claim 11 depends. Nitta teaches wherein the chip is a security chip (para 4, where the RFID label is for security purposes).
Regarding claim 12, Nitta teaches a first paper layer; a second paper layer; and a chip-interconnect arrangement as claimed in claim 1 between the first paper layer and the second paper layer (Fig. 9, paper layers 2 and 7).
Regarding claim 13, Nitta teaches A method for forming a chip-interconnect arrangement, the method comprising: forming a cavity in a substrate (Fig. 2, 6 including 2 - more clearly because 6 includes many elements, the substrate for clarity is specifically 2 and A2, para 7-8); applying an interconnect having an interconnect surface on a surface of the substrate (Fig. 3, 31-36); arranging a chip having at least one chip contact and one chip contact surface in the cavity (Fig. 2, 5 in cavity of 6 specifically layer A2); arranging an electrically conductive adhesion medium between the at least one chip contact and the interconnect (para 48); and shaping the adhesion medium such that the surface of the adhesion medium is planar (Fig. 2, intersection of 5 and 1 planar across x axis).
Regarding claim 14, Nitta teaches the limitations of claim 13 upon which claim 14 depends. Nitta teaches wherein when the chip-interconnect arrangement bears on a horizontal surface with a chip facing away from the surface, and a planar surface of the adhesion medium is substantially parallel to the horizontal surface (Fig. 4, planar surface along x axis, 5 facing away from 2, substantially parallel to x axis).
Regarding claim 15, Nitta teaches the limitations of claim 13 upon which claim 15 depends. Nitta teaches wherein the chip contact surface, the interconnect surface and a surface of the adhesion medium are coplanar with respect to one another or the adhesion medium is coplanar with respect to that surface out of the chip contact surface and the interconnect surface which is further away from a principal plane of the substrate (Fig. 4, 5 contact surface on adhesion medium with interconnects 31, 33, and 35 coplanar along x axis).
Regarding claim 16, Nitta teaches the limitations of claim 13 upon which claim 16 depends. Nitta teaches wherein the shaping comprises pressing the adhesion medium flat (Fig. 4, para 7, "laminated" where pressing is typically part of the lamination process).
Regarding claim 17, Nitta teaches the limitations of claim 13 upon which claim 17 depends. Nitta teaches wherein the shaping comprises applying pressure and/or heat (Fig. 4, para 7, "laminated" where pressing is typically part of the lamination process).
Regarding claim 18, Nitta teaches the limitations of claim 13 upon which claim 18 depends. Nitta teaches embedding the chip-interconnect arrangement between a first paper layer and a second paper layer (Fig. 9, paper layers 2 and 7).
Regarding claim 19, Nitta teaches the limitations of claim 18 upon which claim 19 depends. Nitta teaches wherein the embedding comprises laminating (Fig. 4, para 7, "laminated")
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta (US Publication 20240028861) in view of Oberle (US Publication 20080129455).
Regarding claim 4, Nitta teaches the limitations of claim 1 upon which claim 4 depends. Nitta does not specifically teach wherein the adhesion medium has an isotropic conductive adhesive.
Oberle teaches wherein the adhesion medium has an isotropic conductive adhesive (para 29, conductive adhesive 116, "conventional isotropic conductive adhesive").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Nitta to include an isotropic conductive adhesive as taught by Oberle in order to improve the interoperability and reliability of the device.
Response to Arguments
Applicant's arguments filed 28 October 2025 have been fully considered but they are not persuasive.
Applicant argues that Nitta does not disclose “a substrate having a cavity”, “a chip…arranged in a cavity.”, “an interconnect having and interconnect surface…applied on a surface of the substrate.”, and “an electrically conductive adhesion medium…wherein the adhesion medium comprises a planar surface.”
As to Applicants argument that Nitta does not disclose a substrate with a cavity, elements 3 and 5 are in a cavity of the substrate 2/A2.
As to Applicants argument that an antenna is stretching the meaning of an interconnect, note that the antenna (3) has many elements including an IC chip connection portion 32 (see para 38). Applicant is invited to more clearly define the interconnect, such as specific material, position, etc. to define over the prior art. It is further noted, that in claim 5, applicant states that the interconnect has an antenna.
As to the adhesion medium not specifically being a planar surface – films (paragraph 48 - the anisotropic conductive film) are considered planar because they are two-dimensional surfaces with a negligible thickness compared to their length and width.
One additional note, the phrase "applying on" is broad, it is recommended Applicant make clear exact position of elements with a phrase such as "directly contacting the surface of the substrate".
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818