DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/4/26 has been entered.
Election/Restrictions
Applicant’s election without traverse to the restriction requirement mailed on 8/11/25 of Group I (device claims 1-12) in the reply filed on 10/9/25 was acknowledged in a previous office action. Claims 13-15 were withdrawn and have been canceled by the Applicant.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 5-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 11387142 B1 (“Matsuno”) in view of US 2018/0151490 A1 (“Yim”).
Matsuno teaches, for example:
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Matsuno teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A semiconductor storage device comprising:
a first wiring (e.g. one 118 in e.g. Fig. 15A) extending in a first direction (e.g. perpendicular to the cross-section shown in Fig. 15A);
a second wiring (e.g. another 118 in e.g. Fig. 15A) apart from the first wiring in a second direction (e.g. left-to-right as shown in Fig. 15A) crossing the first direction, the second wiring extending in the first direction.
Matsuno does not explicitly teach:
a first insulating layer having a first portion, a second portion, and a third portion,
the first portion being stacked on the first wiring in a third direction crossing the first direction and the second direction,
the second portion being stacked on the second wiring in the third direction,
the third portion being on an opposite side of the first wiring from the first portion and the second portion,
the third portion being on an opposite side of the second wiring from the second portion,
the third portion extending in the second direction at least over the first portion and the second portion;
a first insulator having a portion between the first portion and the second portion of the first insulating layer in the second direction; and
a conductor extending to the first insulating layer from an opposite side of the first wiring with respect to the first insulating layer,
the conductor having a first conductive portion and a second conductive portion,
the first conductive portion penetrating through the third portion and the first portion of the first insulating layer in the third direction,
the first conductive portion being in contact with the first wiring,
the second conductive portion penetrating through the third portion of the first insulating layer in the third direction,
the second conductive portion being in contact with the first insulator,
the second conductive portion having a level difference portion, the level difference portion being between the first conductive portion and the second conductive portion.
Yim teaches, for example:
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Yim teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Matsuno:
a first insulating layer 70 having
a first portion (e.g. generally being a bottom portion of 70, under the portion identified as the third portion as discussed below; and being on e.g. the top left side of the second-from-left 30 in Fig. 5),
a second portion (e.g. generally being a bottom portion of 70, under the portion identified as the third portion as discussed below; and being on the top side of the fourth-from-left 30 in Fig. 5), and
a third portion (e.g. generally the upper portion of 70, e.g. the top 10%, 20%, 30$, or 50% thereof),
the first portion being stacked on the first wiring (e.g. second-from-left 30 in Fig. 5) in a third direction (bottom-to-top direction as shown in both Yim and Matsuno) crossing the first direction and the second direction,
the second portion being stacked on the second wiring (e.g. fourth-from-left 30 in Fig. 5) in the third direction (bottom-to-top direction as shown in both Yim and Matsuno),
the first portion being between the first wiring and the third portion (Fig. 5),
the second portion being between the second wiring and the third portion (Fig. 5),
the third portion extending in the second direction (e.g. left-to-right in Fig. 5) at least over the first portion and the second portion (see e.g. Fig. 5);
a first insulator (e.g. 80) having a portion between the first portion and the second portion of the first insulating layer in the second direction (80 has a bottom portion thereof that is generally laterally between and generally laterally above the first and second portions of 70); and
a conductor (e.g. the 90 that is labeled in Fig. 5; or parts thereof such as 93a and/or 91) extending to the first insulating layer from an opposite side of the first wiring with respect to the first insulating layer (90 extends from the very top of 80 to its very bottom, and passes through 70, see e.g. Fig. 5),
the conductor having a first conductive portion (e.g. left bottom portion thereof) and a second conductive portion (e.g. right bottom portion thereof),
the first conductive portion penetrating through the third portion (the left side of 90 extends through the top of 70) and the first portion (90 extends through the portion of 70b on the top of 30) of the first insulating layer in the third direction,
the first conductive portion being in contact with the first wiring (see e.g. Fig. 5),
the second conductive portion penetrating through the third portion of the first insulating layer in the third direction (the right side of 90 penetrates through 70),
the second conductive portion being in contact with the first insulator (the left side of 90 is in contact with 80),
the second conductive portion having a level difference portion (portion of 90 or 93a having a step in the left side thereof, rather than a single continuous linear slope), the level difference portion being between the first conductive portion and the second conductive portion (see e.g. Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Yim to the invention of Matsuno. The motivation to do so is that the combination produces the predictable results of forming self-aligned contacts (see e.g. para 70) to technologies having highly-integrated, high-speed semiconductor devices with a reduced critical dimension (see e.g. para 3) in a way that does not suffer from increased electrical resistance or capacitive coupling (see e.g. para 3).
Matsuno and Yim together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
2. The semiconductor storage device according to claim 1, wherein
the first insulator includes a first insulating material containing oxygen (see in Yim wherein e.g. 80 may comprise silicon oxide, para 44), and
the first portion, the second portion, and the third portion of the first insulating layer include a second insulating material containing nitrogen (see in Yim wherein e.g. 70 may comprise silicon nitride, silicon oxynitride, or silicon carbonitride, para 44).
Applicant has not disclosed that the claimed materials are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
3. The semiconductor storage device according to claim 1, wherein
the first insulator includes a first insulating material containing oxygen (see in Yim wherein e.g. 80 may comprise silicon oxide, para 44),
the first portion and the second portion of the first insulating layer include a second insulating material containing nitrogen (see in Yim wherein e.g. 70 may comprise silicon nitride, silicon oxynitride, or silicon carbonitride, para 44),
the third portion of the first insulating layer includes a third insulating material, the third insulating material contains nitrogen (see in Yim wherein e.g. 70 may comprise silicon nitride, silicon oxynitride, or silicon carbonitride, para 44), and
the third insulating material is different from the second insulating material (see e.g. para 41 wherein 70 may be formed from one or more of SiN, SiON, SiCN, etc.; if it is formed by more than one, it is obvious to form a bilayer of materials, as that is known in the art; thus, the third portion, at the top of 70, would be formed of a different material than the first and second portions, at the bottom of 70).
Applicant has not disclosed that the claimed materials are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
5. The semiconductor storage device according to claim 1, wherein the first wiring (e.g. Yim’s 30 or Matsuno’s 118) has a first end (e.g. top of Yim’s 30 or top of Matsuno’s 118) and a second end (e.g. bottom), the second end is on an opposite side of the first end in the third direction (top vs. bottom), the first end is closer to the first insulating layer than to the second end (the distance from the top of 30 to 70 is smaller than the distance from the bottom of 30 to 70 in Yim; when adding 70 to Matsuno, the same would be true), and
a width of the second end in the second direction is larger than a width of the first end in the second direction (this is taught in Matsuno, wherein the bottom of 118 is wider than the top of 118, see e.g. Fig. 15A or 31B).
The shapes of 118 in Matsuno can easily be maintained while adding e.g. Yim’s layer 70 and 90 thereto. All that would need to occur is to form 30 having Matsuno’s shape in Yim’s Fig. 2A, and the remainder of the manufacturing steps shown in Figs. 2B-2F would still be followed.
6. The semiconductor storage device according to claim 5, wherein the first wiring is formed in a shape on one cross section parallel to the second direction and the third direction, and a width of the first wiring in the second direction gradually increases in a direction from the first end to the second end (see the shape of 118 in e.g. Matsuno’s Fig. 15A or 31B).
7. The semiconductor storage device according to claim 6, wherein the first wiring is formed in a trapezoid shape (see the shape of 118 in e.g. Matsuno’s Fig. 23B).
8. The semiconductor storage device according to claim 1,
further comprising: a multi-layered body (see many layers e.g. 46, 32, etc. in Fig. 15) on an opposite side of the first insulating layer from one of the first wiring and the second wiring (they are on the bottom thereof), the multi-layered body including a plurality of gate electrode layers (e.g. 46, which “can function as… control gate electrodes… and a word line…”) and a plurality of second insulating layers (e.g. 32 and/or 70), the plurality of the gate electrode layers and the plurality of the second insulating layers being alternately stacked one by one in the third direction (see e.g. Fig. 15A); and
a columnar body (e.g. “memory stack structure 55” or portions thereof) extending in the third direction inside the multi-layered body,
the columnar body including an insulating core (e.g. “dielectric core 62” see e.g. Figs. 5H and 15A), a channel layer (e.g. “”vertical semiconductor channel 60” see e.g. Figs. 5H and 15A), and a memory film (e.g. “memory film 50” or a portion thereof), the channel layer being between the plurality of the gate electrode layers and the insulating core (see e.g. Figs. 5H and 15A), the columnar body being between the plurality of the gate electrode layers and the channel layer (see e.g. Figs. 5H and 15A).
9. The semiconductor storage device according to claim 8, wherein the first wiring is a bit line (“bit lines 118”) electrically connected to the channel layer of the columnar body (see e.g. Fig. 15A).
10. The semiconductor storage device according to claim 8, wherein the first wiring has a first side end (e.g. top) and a second side end (e.g. bottom) on one cross section parallel to the second direction and the third direction, the first side end being in contact with the first insulator (see Yim’s Fig. 5), the second side end being on an opposite side of the first side end (top vs. bottom), and an inside of the first wiring is uniform over a region between the first side end and the second side end (the material of Matsuno’s 118 and the material of Yim’s 33 are not disclosed to not be uniform; it is thus obvious that it is uniform).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
11. The semiconductor storage device according to claim 8, wherein a line extending in the second direction along a boundary between the third portion of the first insulating layer and the first insulator on one cross section parallel to the second direction and the third direction is a first virtual line, an inside of the first insulating layer is uniform in a region between the first virtual line and the second wiring at least in the third direction (note, there are no disclosed non-uniformities in e.g. material of the first insulating layer, so there would be no non-uniformities in this region).
12. The semiconductor storage device according to claim 8, wherein the third portion of the first insulating layer has a first surface (e.g. top of 70 above the top of 65) and a second surface (e.g. bottom of 70 above the top of 65), the first surface being in contact with the first insulator 80 in the third direction, the second surface being on an opposite side of the first surface (top vs. bottom), and the second surface does not have a recess having a depth greater than 10 nm in the third direction on a region overlapping the second wiring when viewed from the first direction on one cross section parallel to the second direction and the third direction (there is no recess in the portion of 70 directly touching the topmost vertical portion of 65).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 11387142 B1 (“Matsuno”) in view of US 2018/0151490 A1 (“Yim”) and US 2009/0294976 A1 (“Lee”).
Re claim 4, Matsuno and Yim teach claim 1 and further teach and/or suggest as obvious: a third wiring (e.g. 93a) on an opposite side of the first wiring (e.g. 93b) with respect to the conductor, the third wiring being connected to the conductor (at the dotted line between 93a and 93b), the third wiring extending in the first direction or the second direction (see e.g. Fig. 5).
Matsuno and Yim do not teach a second insulator between the third wiring and the first insulating layer at a position out of the conductor, the second insulator including a fourth insulating material containing oxygen.
Lee teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Matsuno and Yim, a second insulator between the third wiring and the first insulating layer at a position out of the conductor, the second insulator including a fourth insulating material containing oxygen (see e.g. para 80 wherein a nitride oxide film or an oxide film is formed on the sides of the bit line barrier metal film, reducing parasitic capacitance of the bit lines).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Lee to the invention of Matsuno and Yim. The motivation to do so is that the combination produces the predictable results of reducing parasitic capacitance of the bit lines (see e.g. para 80).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are not persuasive. Applicant envisions 5 interpretations and attempts to rebut them (see 8/4/26 remarks, pages 9-13). These are hypothetical interpretations that do not match the interpretation taken in the rejection above. Hence, there is no need to respond to them.
While Applicant labels in e.g. Fig. 6 first portion 81-1, second portion 81-2, and third portion 82, the portions are essentially arbitrary. The third portion, while labeled as a small rectangle 82 only directly above 81-2, could well extend over the entire G1 layer from left to right. In fact, in the claims, it is required to be above the first portion 81-1 and hence extends well beyond the area in the rectangle that is shown. The claim does not define the geometrical boundaries, materials, or other characteristics of the first, second, or third portions. The specification allows for them to be all the same material in one continuous body, without boundary (see e.g. para 75 of the published application US 2024/0096795 A1). Hence, it is reasonable in Yim to interpret the top region of 70 (e.g. the top 10%, or 30%, thereof), from the leftmost part of Fig. 5 to the rightmost part of Fig. 5, as a “third portion”. This is thus above many choices of the “first portion”, which is generally the bottom region of 70 above one of the left wirings 33, and above many choices of the “second portion”, which is generally also the bottom region of 70 above one of the right wirings 33. This thus reads on the claimed geometry.
Conclusion
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
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