CTFR 18/182,765 CTFR 84435 DETAILED ACTION Election/Restrictions Applicant’s election without traverse to the restriction requirement mailed on 10/27/25 of Group I (device claims 1-5 and 10-12) and species DA (Figs. 1-4 and 17), in the reply filed on 12/23/25 was acknowledged in a previous office action. Claims 6-9 and 12 are withdrawn. Foreign Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), first paragraph: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 Claim(s) 1-5 and 10-11 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph , as failing to comply with the written description requirement. The claim(s) contains subject matter (i.e. “new matter") which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 has been amended to recite: 1. A semiconductor storage device comprising: a plurality of memory cell array layers stacked in a stacking direction of the semiconductor storage device, wherein each of the plurality of the memory cell array layers has a first surface and a second surface, the second surface is on an opposite side of the first surface, each of the plurality of the memory cell array layers does not include a substrate, each of the plurality of the memory cell array layers includes a memory cell array region, a plurality of memory cells, a first surface interconnection layer, a second surface interconnection layer, and a signal-line electrode, the plurality of the memory cells are three-dimensionally in the memory cell array region, the first surface interconnection layer is embedded in the first surface , the second surface interconnection layer is embedded in the second surface , the signal-line electrode connects the first surface interconnection layer and the second surface interconnection layer , each of the plurality of the memory cells includes a multi-layered body, the multi-layered body includes a plurality of insulating layers and a plurality of electrode layers, the plurality of the insulating layers and the plurality of the electrode layers are alternately stacked one by one, the multi-layered body has a staircase structure including an inclined portion, the staircase structure includes a contact plug extending in the stacking direction, each of the plurality of the memory cell array layers includes an inner interconnection layer extending in a direction crossing the stacking direction, the inner connection layer connects the contact plug and the signal-line electrode, the plurality of the electrode layers have a plurality of end portions corresponding one-to-one to the plurality of the electrode layers, each of the plurality of end portions is connected to the contact plug , each of the plurality of electrode layers is electrically connected to the first surface interconnection layer and the second surface interconnection layer via the contact plug , the inner interconnection layer, and the signal-line electrode , positions of the plurality of the end portions are displaced from each other for each stacked position in the staircase structure when viewed from a stacking direction of the multi-layered body, the plurality of the memory cell array layers are stacked such that two memory cell array layers adjacent to each other in the stacking direction are connected to each other via the first surface interconnection layer and the second surface interconnection layer, the two memory cell array layers adjacent to each other have a multi-layered boundary surface therebetween, and the inclined portion of each of the two memory cell array layers adjacent to each other faces the multi-layered boundary surface. Claim 10 has been amended to recite: 10. A semiconductor wafer, comprising: a first wafer including a first substrate and a first memory cell array layer, the first memory cell array layer being on the first substrate, the first memory cell array layer including a first memory cell array region, a plurality of first memory cells, and a first surface interconnection layer, the plurality of the first memory cells being three-dimensionally on the first memory cell array region; and a second wafer including a second substrate and a second memory cell array layer, the second memory cell array layer being on the second substrate, the second memory cell array layer including a second memory cell array region, a plurality of second memory cells, and a second surface interconnection layer, the plurality of the second memory cells being three-dimensionally on the second memory cell array region, wherein the first substrate and the second substrate are bonded to each other in a stacking direction of the semiconductor wafer, the first substrate and the second substrate have a multi-layered boundary surface therebetween, and the first substrate is bonded to the second substrate such that the first surface interconnection layer is connected to the second surface interconnection layer at the multi-layered boundary surface, and wherein each of the first memory cell array layer and the second memory cell array layer includes a signal-line electrode extending in the stacking direction, the signal-line electrode of the first memory cell array layer is connected to the first surface interconnection layer, the signal-line electrode of the second memory cell array layer is connected to the second surface interconnection layer, each of the first memory cell array layer and the second memory cell array layer includes a multi-layered body, the multi-layered body includes a plurality of insulating layers and a plurality of electrode layers, the plurality of the insulating layers and the plurality of the electrode layers are alternately stacked one by one, the multi-layered body has a staircase structure including an inclined portion, the staircase structure includes a contact plug extending in the stacking direction, each of the plurality of the memory cell array layers includes an inner interconnection layer extending in a direction crossing the stacking direction, the inner interconnection layer connects the contact plug and the signal-line electrode, the plurality of the electrode layers have a plurality of end portions corresponding one-to-one to the plurality of the electrode layers, each of the plurality of end portions is connected to the contact plug , and each of the plurality of the electrode layers is electrically connected to the first surface interconnection layer and the second surface interconnection layer via the contact plug , the inner interconnection layer, and the signal-line electrode. Thus, each of claims 1 and 10 have been newly amended to require each end portion of word lines such as WL1, WL2, …, WLN to be connected to a single contact plug 30. However, as can be seen in Fig. 1 (see partial view thereof below), the specification discloses that each word line connects to a different contact plug. Thus, the claim contains “new matter”. Thus, each of claims 1 and 10 have been newly amended to require each of the plurality of electrode layers (e.g. WL1, WL2, …, WLN, as identified in the specification) to be electrically connected to the first surface interconnection layer and the second surface interconnection layer (e.g. 38a and 39a) via the (single) contact plug 30, the (single) inner interconnection layer (e.g. probably 35 or 36), and the (single) signal-line electrode (e.g. 37a or 37b, as identified in the specification). However, as can be seen in Fig. 1 (see partial view thereof below), the specification discloses that each word line connects to a different contact plug, some of which connect to the same lines 33, 34, 35, and 36, but others connect to different ones of 33, 34, 35, and 36. Thus, the claim contains “new matter”. Claims 2-5 depend from claim 1 and inherit its deficiencies. Claim 11 depend from claim 10 and inherit its deficiencies. FIG 1, annotated by zooming to show only part of the figure PNG media_image1.png 775 525 media_image1.png Greyscale Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim(s) 1-5 and 10-11 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph , as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention. Claim 1 has been amended to recite: 1. A semiconductor storage device comprising: a plurality of memory cell array layers stacked in a stacking direction of the semiconductor storage device, wherein each of the plurality of the memory cell array layers has a first surface and a second surface, the second surface is on an opposite side of the first surface, each of the plurality of the memory cell array layers does not include a substrate, each of the plurality of the memory cell array layers includes a memory cell array region, a plurality of memory cells, a first surface interconnection layer, a second surface interconnection layer, and a signal-line electrode, the plurality of the memory cells are three-dimensionally in the memory cell array region, the first surface interconnection layer is embedded in the first surface , the second surface interconnection layer is embedded in the second surface , the signal-line electrode connects the first surface interconnection layer and the second surface interconnection layer , each of the plurality of the memory cells includes a multi-layered body, the multi-layered body includes a plurality of insulating layers and a plurality of electrode layers, the plurality of the insulating layers and the plurality of the electrode layers are alternately stacked one by one, the multi-layered body has a staircase structure including an inclined portion, the staircase structure includes a contact plug extending in the stacking direction, each of the plurality of the memory cell array layers includes an inner interconnection layer extending in a direction crossing the stacking direction, the inner connection layer connects the contact plug and the signal-line electrode, the plurality of the electrode layers have a plurality of end portions corresponding one-to-one to the plurality of the electrode layers, each of the plurality of end portions is connected to the contact plug , each of the plurality of electrode layers is electrically connected to the first surface interconnection layer and the second surface interconnection layer via the contact plug , the inner interconnection layer, and the signal-line electrode , positions of the plurality of the end portions are displaced from each other for each stacked position in the staircase structure when viewed from a stacking direction of the multi-layered body, the plurality of the memory cell array layers are stacked such that two memory cell array layers adjacent to each other in the stacking direction are connected to each other via the first surface interconnection layer and the second surface interconnection layer, the two memory cell array layers adjacent to each other have a multi-layered boundary surface therebetween, and the inclined portion of each of the two memory cell array layers adjacent to each other faces the multi-layered boundary surface. Claim 10 has been amended to recite: 10. A semiconductor wafer, comprising: a first wafer including a first substrate and a first memory cell array layer, the first memory cell array layer being on the first substrate, the first memory cell array layer including a first memory cell array region, a plurality of first memory cells, and a first surface interconnection layer, the plurality of the first memory cells being three-dimensionally on the first memory cell array region; and a second wafer including a second substrate and a second memory cell array layer, the second memory cell array layer being on the second substrate, the second memory cell array layer including a second memory cell array region, a plurality of second memory cells, and a second surface interconnection layer, the plurality of the second memory cells being three-dimensionally on the second memory cell array region, wherein the first substrate and the second substrate are bonded to each other in a stacking direction of the semiconductor wafer, the first substrate and the second substrate have a multi-layered boundary surface therebetween, and the first substrate is bonded to the second substrate such that the first surface interconnection layer is connected to the second surface interconnection layer at the multi-layered boundary surface, and wherein each of the first memory cell array layer and the second memory cell array layer includes a signal-line electrode extending in the stacking direction, the signal-line electrode of the first memory cell array layer is connected to the first surface interconnection layer, the signal-line electrode of the second memory cell array layer is connected to the second surface interconnection layer, each of the first memory cell array layer and the second memory cell array layer includes a multi-layered body, the multi-layered body includes a plurality of insulating layers and a plurality of electrode layers, the plurality of the insulating layers and the plurality of the electrode layers are alternately stacked one by one, the multi-layered body has a staircase structure including an inclined portion, the staircase structure includes a contact plug extending in the stacking direction, each of the plurality of the memory cell array layers includes an inner interconnection layer extending in a direction crossing the stacking direction, the inner interconnection layer connects the contact plug and the signal-line electrode, the plurality of the electrode layers have a plurality of end portions corresponding one-to-one to the plurality of the electrode layers, each of the plurality of end portions is connected to the contact plug , and each of the plurality of the electrode layers is electrically connected to the first surface interconnection layer and the second surface interconnection layer via the contact plug , the inner interconnection layer, and the signal-line electrode. The metes and bounds of the claimed limitations of claims 1 and 10 can not be determined for the following reasons: The claims set forth that “ each of the plurality of end portions is connected to the contact plug” and “each of the plurality of the electrode layers is electrically connected to the first surface interconnection layer and the second surface interconnection layer via the contact plug , the inner interconnection layer, and the signal-line electrode”, though Fig. 1 shows that each word line WL connects to a different contact plug 30; and some 30s connect to the same line 33, 34, 35, or 36, but other 30s connect to different ones of 33, 34, 35, or 36; and some of 33, 34, 35, and 36 connect to a single 37a, but others connect to a different 37a. Thus, Fig. 1 does not show the claimed limitations, and by disagreeing with the claimed limitations, it is unclear exactly what is required of each word line, each contact plug, each line 33-36, and each signal-line drawing electrode 37a. Furthermore, while the claims often refer to “each” of plural items, and/or refer to a plurality of items, but then refer to only one of the items, making it unclear if the reference to only one of the items really only is required of a single item or if it is required by each of them, or if it is required by the plurality of them. For example, the claim requires “ each of the plurality of the memory cell array layers includes a memory cell array region, a plurality of memory cells, a first surface interconnection layer, a second surface interconnection layer, and a signal-line electrode, the plurality of the memory cells are three-dimensionally in the memory cell array region, the first surface interconnection layer [singular] is embedded in the first surface, the second surface interconnection layer [singular] is embedded in the second surface, the signal-line electrode [singular] connects the first surface interconnection layer and the second surface interconnection layer”, so it is unclear if the claim requires each first surface interconnection layer is embedded in the first surface, if it requires each the second surface interconnection layer is embedded in the second surface, and if it requires each signal-line electrode connects the first surface interconnection layer and the second surface interconnection layer, or if a stacked situation wherein only one of these meets the claimed requirement satisfies the claim. Claims 2-5 depend from claim 1 and inherit its deficiencies. Claim 11 depend from claim 10 and inherit its deficiencies. 07-30-03-h AIA Claim Interpretation The applicant is hereby notified that the examiner is treating claims 4 and 10-11 as "product-by-process” claims. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” (See In re Thorpe , 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), and also see MPEP 2113). The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. (See, e.g., In re Garnero, 412 F.2d 276, 279, 162 USPQ 221, 223 (CCPA 1979) and also see MPEP 2113). Claim 4 recites the limitation “… the multi-layered boundary surface is a bonded surface, and the two memory cell array layers adjacent to each other are bonded to each other at the bonded surface…” , which includes the result of a process (“bonding”), despite being device a claim. The process of “bonding” results in two objects merely being connected together. Such connection could be achieved by many different processes, such as “direct” bonding, bonding using intermediate substances such as adhesives, or direct formation of a second material on a first material. Thus, the distinctive structural characteristic of this limitation is that there is a multi-layered boundary surface having two memory cell array layers adjacent to each other being connected, either directly or indirectly, at said surface. Claim 10 recites the limitation “the first substrate and the second substrate are bonded to each other…”, which includes the result of a process (“bonding”), despite being a device claim. The process of “bonding” results in two objects merely being connected together. Such connection could be achieved by many different processes, such as “direct” bonding, bonding using intermediate substances such as adhesives, or direct formation of a second material on a first material. Thus, the distinctive structural characteristic of this limitation is the first substrate and the second substrate are connected together, either directly or indirectly. Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. (See In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)). Also note the use of 102/103 rejections for product-by-process claims has been approved by the courts. (See In re Brown , 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972), and also see MPEP 2113). Claims 11-12 depend from claim 10 and inherit its product-by-process identification. Response to Arguments Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection. Conclusion Conclusion / Finality 07-40 AIA Applicant's amendment changed the scope of the claims and necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Conclusion / Prior Art The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited. Conclusion / Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Kevin Parendo/Primary Examiner, Art Unit 2896 Application/Control Number: 18/182,765 Page 2 Art Unit: 2896 Application/Control Number: 18/182,765 Page 3 Art Unit: 2896 Application/Control Number: 18/182,765 Page 4 Art Unit: 2896 Application/Control Number: 18/182,765 Page 5 Art Unit: 2896 Application/Control Number: 18/182,765 Page 6 Art Unit: 2896 Application/Control Number: 18/182,765 Page 7 Art Unit: 2896 Application/Control Number: 18/182,765 Page 8 Art Unit: 2896 Application/Control Number: 18/182,765 Page 9 Art Unit: 2896 Application/Control Number: 18/182,765 Page 10 Art Unit: 2896 Application/Control Number: 18/182,765 Page 11 Art Unit: 2896 Application/Control Number: 18/182,765 Page 12 Art Unit: 2896 Application/Control Number: 18/182,765 Page 13 Art Unit: 2896 Application/Control Number: 18/182,765 Page 14 Art Unit: 2896 Application/Control Number: 18/182,765 Page 15 Art Unit: 2896 Application/Control Number: 18/182,765 Page 16 Art Unit: 2896 Application/Control Number: 18/182,765 Page 17 Art Unit: 2896
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