DETAILED ACTION
Election/Restrictions
A restriction requirement was mailed on 10/27/25.
Applicant’s election without traverse of Group I (device claims 1-5 and 10-12) and species DA (Figs. 1-4 and 17) in the reply filed on 12/23/25 is acknowledged.
Claims 6-9 and 12 are withdrawn because claims 6-9 read on nonelected Group II and claim 12 does not read on elected species DA, having claimed features corresponding to the various types of trimmed portions that are shown in Figs. 6-8 and 12-14.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Direct-bonded semiconductor storage device
Claim Objections
While it is withdrawn at this time, in the case that it is ultimately rejoined, claim 12 is objected to because the typographical error “…innder circumferential…” should be changed to “…inner circumferential...”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claim 5 recites the limitation “a plurality of drawing portions…”. The metes and bounds of the claimed limitation can not be determined for the following reasons: the term “drawing portion” is not clear. It is not a term of art. The specification does not define it. The specification uses the term, but only in examples, wherein elements 35 and 36 are described as “drawing portions”, but the specification gives no criteria as to what properties a “drawing portion” has or what criteria determine whether an element is a “drawing portion.”
Claim Interpretation
The applicant is hereby notified that the examiner is treating claims 4 and 10-11 as "product-by-process” claims. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” (See In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), and also see MPEP 2113).
The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. (See, e.g., In re Garnero, 412 F.2d 276, 279, 162 USPQ 221, 223 (CCPA 1979) and also see MPEP 2113).
Claim 4 recites the limitation “…the multi-layered boundary surface is a bonded surface, and the two memory cell array layers adjacent to each other are bonded to each other at the bonded surface…”, which includes the result of a process (“bonding”), despite being device a claim. The process of “bonding” results in two objects merely being connected together. Such connection could be achieved by many different processes, such as “direct” bonding, bonding using intermediate substances such as adhesives, or direct formation of a second material on a first material. Thus, the distinctive structural characteristic of this limitation is that there is a multi-layered boundary surface having two memory cell array layers adjacent to each other being connected, either directly or indirectly, at said surface.
Claim 10 recites the limitation “the first substrate and the second substrate are bonded to each other”, which includes the result of a process (“bonding”), despite being a device claim. The process of “bonding” results in two objects merely being connected together. Such connection could be achieved by many different processes, such as “direct” bonding, bonding using intermediate substances such as adhesives, or direct formation of a second material on a first material. Thus, the distinctive structural characteristic of this limitation is the first substrate and the second substrate are connected together, either directly or indirectly.
Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. (See In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)).
Also note the use of 102/103 rejections for product-by-process claims has been approved by the courts. (See In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972), and also see MPEP 2113).
Claims 11-12 depend from claim 10 and inherit its product-by-process identification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 and 10-11 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2021/0202458 A1 (“Jung”).
Jung teaches, for example:
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Jung teaches:
1. A semiconductor storage device comprising:
a plurality of memory cell array layers (e.g. CS2 and CS3, see e.g. Fig. 9),
wherein
each of the plurality of the memory cell array layers has a first surface and a second surface, the second surface is on an opposite side of the first surface (e.g. CS2 and CS3 each have opposing top and bottom surfaces),
each of the plurality of the memory cell array layers does not include a substrate (each of CS2 and CS3 themselves lack a substrate such as 10, which is only in CS1, see e.g. para 32),
each of the plurality of the memory cell array layers includes a memory cell array region (e.g. region having memory cells, e.g. MCA, see e.g. para 26), a plurality of memory cells (see e.g. para 26, 76, 171), and a surface interconnection layer (e.g. CS2 and CS3 each have a layer generally at the interface between CS2 and CS3, having 170 or 170’, 120 or 120’, perhaps 160 or 160’, and perhaps portions of 120 or 120’ therein),
the plurality of the memory cells are three-dimensionally in the memory cell array region (see e.g. Fig. 9, para 76),
the surface interconnection layer is embedded in the first surface and the second surface (see e.g. Fig. 9),
each of the plurality of the memory cells includes a multi-layered body (see e.g. Fig. 9), the multi-layered body includes a plurality of insulating layers (see e.g. 120, parts of 120, 120a, 120b, 120c, 120d, see e.g. para 37-38) and a plurality of electrode layers (see e.g. 150, ),
the plurality of the insulating layers and the plurality of the electrode layers are alternately stacked one by one (see e.g. Fig. 9 and para 46),
the multi-layered body has a staircase structure including an inclined portion (see e.g. Fig. 9, wherein various layers 150 have a generally staircase-shaped arrangement, with the ends of 150 being geometrically arranged in a line inclined with respect to the horizontal surface of 10),
the plurality of the electrode layers have a plurality of end portions corresponding one-to-one to the plurality of the electrode layers (each electrode layer 50 has such an end, see e.g. Fig. 9),
positions of the plurality of the end portions are displaced from each other for each stacked position in the staircase structure when viewed from a stacking direction of the multi-layered body (see e.g. Fig. 9, wherein in side view, the ends have a staircase structure; when viewed from a stacking direction, they would also thus have such a staircase structure),
the plurality of the memory cell array layers are stacked such that two memory cell array layers adjacent to each other in the stacking direction are connected to each other via the surface interconnection layer (see e.g. Fig. 9),
the two memory cell array layers adjacent to each other have a multi-layered boundary surface therebetween (see wherein 170 and 170’ contact each other, and 120 and 120’ contact each other, at multiple positions along the boundary line between CS2 and CS3 in Fig. 9), and
the inclined portion of each of the two memory cell array layers adjacent to each other faces the multi-layered boundary surface (see e.g. Fig. 9, wherein the inclines face each other).
2. The semiconductor storage device according to claim 1, further comprising:
a control circuit layer (e.g. CS1, see e.g. para 25-28) comprising a circuit substrate (e.g. 10), a control circuit (e.g. PC, see e.g. para 26-28), and a circuit-side surface interconnection layer (e.g. planar surface that forms the interface between CS1 and CS3, and/or the features at that planar surface, such as 30 and 20b),
the circuit substrate having a circuit-formed surface (see e.g. top of 10 in Fig. 9),
the control circuit being on the circuit-formed surface (see e.g. Fig. 9),
the circuit-side surface interconnection layer being on the circuit-formed surface and being electrically connected to the control circuit (see e.g. Fig. 9),
wherein
the plurality of the memory cell array layers includes a first memory cell array layer stacked on the control circuit layer (see e.g. memory cells in CS3),
the first memory cell array layer includes a first surface interconnection layer corresponding to the surface interconnection layer (see e.g. wherein 192 meet 30 in Fig. 9), and
the first surface interconnection layer is connected to the circuit-side surface interconnection layer (see e.g. wherein 192 meet 30 in Fig. 9).
3. The semiconductor storage device according to claim 1, further comprising:
a bit line (e.g. “bitline structure 160”, see e.g. para 60); a source line (e.g. “source wiring structure 164”, see e.g. para 60); and a source-side interconnection layer at a position adjacent to the source line,
wherein each of the plurality of the memory cells includes a columnar part extending in the stacking direction, the columnar part has a first end and a second end, the second end is on an opposite of the first end, the bit line is electrically connected to the first end, and the source line is electrically connected to the second end.
4. The semiconductor storage device according to claim 1, wherein
the multi-layered boundary surface is a bonded surface, and the two memory cell array layers adjacent to each other are bonded to each other at the bonded surface (see e.g. Fig. 9; see “claim interpretation” section above).
5. The semiconductor storage device according to claim 1, further comprising:
a plurality of interconnections (see e.g. 162 and 162’ in Fig. 9) connected to the plurality of the end portions of the plurality of the electrode layers in the staircase structure in one-to-one correspondence; and a plurality of drawing portions (see 112 rejection, above; see e.g. 162b, 164b, and 166b in Fig. 8, which are various types of “connection patterns”, see e.g. para 62-63; each of these is in Fig. 9, though they are not explicitly labeled there) connected to the plurality of the interconnections in one-to-one correspondence, wherein the plurality of the drawing portions are closer to the multi-layered boundary surface than the plurality of the end portions of the plurality of the electrode layers (each features 162b, 164b, 166b in Fig. 9 in CS2 and in CS3 is closer to the interface between CS2 and CS3 than the ends of 150).
10. A semiconductor wafer, comprising:
a first wafer (e.g. CS1/CS3, see e.g. Fig. 9) including a first substrate (e.g. 10, or 10/20a, or 10/20a/20b, etc.) and a first memory cell array layer (e.g. CS3),
the first memory cell array layer being on the first substrate (see e.g. Fig. 9),
the first memory cell array layer including a first memory cell array region (e.g. region having memory cells, e.g. MCA, see e.g. para 26), a plurality of first memory cells (see e.g. para 26, 76, 171), and a first surface interconnection layer (e.g. a layer generally at the interface between CS2 and CS3, having 170’, 120’, perhaps 160’, and perhaps portions of 120’ therein),
the plurality of the first memory cells being three-dimensionally on the first memory cell array region (see e.g. Fig. 9, para 76); and
a second wafer (e.g. CS2) including a second substrate (e.g. 185; the material and properties of the substrate have not been set forth, and a substrate is merely a layer that may support other layers and/or have other layers formed thereon) and a second memory cell array layer (e.g. portion of CS2 containing memory cells),
the second memory cell array layer being on the second substrate (see e.g. Fig. 9),
the second memory cell array layer including a second memory cell array region (e.g. region having memory cells, e.g. MCA, see e.g. para 26), a plurality of second memory cells (see e.g. para 26, 76, 171), and a second surface interconnection layer (e.g. a layer generally at the interface between CS2 and CS3, having 170, 120, perhaps 160, and perhaps portions of 120 therein),
the plurality of the second memory cells being three-dimensionally on the second memory cell array region (see e.g. Fig. 9, para 76),
wherein
the first substrate and the second substrate are bonded to each other (see claim interpretation section, above; see e.g. Fig. 9),
the first substrate and the second substrate have a multi-layered boundary surface therebetween (see e.g. 120, parts of 120, 120a, 120b, 120c, 120d, see e.g. para 37-38), and
the first substrate is bonded to the second substrate such that the first surface interconnection layer is connected to the second surface interconnection layer at the multi-layered boundary surface (see wherein 170 and 170’ contact each other, and 120 and 120’ contact each other, at multiple positions along the boundary line between CS2 and CS3 in Fig. 9).
11. The semiconductor wafer according to claim 10, wherein
the first memory cell array layer includes a first multi-layered body (see e.g. Fig. 9),
the first multi-layered body includes a plurality of first insulating layers (see e.g. 120, parts of 120, 120a, 120b, 120c, 120d, see e.g. para 37-38) and a plurality of first electrode layers (see e.g. 150),
the plurality of the first insulating layers and the plurality of the first electrode layers are alternately stacked one by one (see e.g. Fig. 9 and para 46),
the first multi-layered body has a first staircase structure including a first inclined portion (see e.g. Fig. 9, wherein various layers 150 have a generally staircase-shaped arrangement, with the ends of 150 being geometrically arranged in a line inclined with respect to the horizontal surface of 10),
the plurality of the first electrode layers have a plurality of first end portions corresponding one-to-one to the plurality of the first electrode layers (each electrode layer 50 has such an end, see e.g. Fig. 9),
positions of the plurality of the first end portions are displaced from each other for each stacked position in the first staircase structure when viewed from a stacking direction of the first multi-layered body (see e.g. Fig. 9, wherein in side view, the ends have a staircase structure; when viewed from a stacking direction, they would also thus have such a staircase structure),
the second memory cell array layer includes a second multi-layered body (see e.g. Fig. 9),
the second multi-layered body includes a plurality of second insulating layers (see e.g. 120, parts of 120, 120a, 120b, 120c, 120d, see e.g. para 37-38) and a plurality of second electrode layers (see e.g. 150),
the plurality of the second insulating layers and the plurality of the second electrode layers are alternately stacked one by one (see e.g. Fig. 9 and para 46),
the second multi-layered body has a second staircase structure including a second inclined portion (see e.g. Fig. 9, wherein various layers 150 have a generally staircase-shaped arrangement, with the ends of 150 being geometrically arranged in a line inclined with respect to the horizontal surface of 10),
the plurality of the second electrode layers have a plurality of second end portions corresponding one-to-one to the plurality of the second electrode layers (each electrode layer 50 has such an end, see e.g. Fig. 9),
positions of the plurality of the second end portions are displaced from each other for each stacked position in the second staircase structure when viewed from a stacking direction of the second multi-layered body (see e.g. Fig. 9, wherein in side view, the ends have a staircase structure; when viewed from a stacking direction, they would also thus have such a staircase structure), and
the first inclined portion of the first staircase structure and the second inclined portion of the second staircase structure face the multi-layered boundary surface (see e.g. Fig. 9, wherein the inclines face each other).
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896