DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/2/26 has been entered.
Election/Restrictions
Applicant’s election without traverse to the restriction requirement mailed on 10/27/25 of Group I (device claims 1-5 and 10-12) and species DA (Figs. 1-4 and 17), in the reply filed on 12/23/25 was acknowledged in a previous office action.
Claims 6-9 and 12 were withdrawn previously, with the 2/26/26 office action including claims 10-11. Further consideration is given to this herein. Because claim 10 requires each wafer to have a “substrate”, it is more logical that the substrate refers to Applicant’s element 1. In other words, it is a true substrate, made of e.g. silicon, and is not merely another layer or a portion of 200 or 300.
As such, the Office hereby withdraws also claims 10-11. Applicant has originally indicated these claims as being withdrawn (see remarks, field 12/23/25, at the time of election).
Hence, claims 6-12 are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claim 1 recites:
1. A semiconductor storage device comprising:
a plurality of memory cell array layers stacked in a stacking direction of the semiconductor storage device,
wherein
each of the plurality of the memory cell array layers has a first surface and a second surface, the second surface is on an opposite side of the first surface,
each of the plurality of the memory cell array layers does not include a substrate,
each of the plurality of the memory cell array layers includes a memory cell array region, a plurality of memory cells, a first surface interconnection layer, a second surface interconnection layer, and a plurality of signal-line electrodes,
the plurality of the memory cells are three-dimensionally in the memory cell array region,
the first surface interconnection layer is embedded in the first surface,
the second surface interconnection layer is embedded in the second surface,
the plurality of signal-line electrodes extend in the stacking direction,
the plurality of signal-line electrodes include at least a first signal-line electrode and a second signal-line electrode,
the plurality of signal-line electrodes connect the first surface interconnection layer and the second surface interconnection layer,
each of the plurality of the memory cells includes a multi-layered body, the multi-layered body includes a plurality of insulating layers and a plurality of electrode layers,
the plurality of the insulating layers and the plurality of the electrode layers are alternately stacked one by one,
the multi-layered body has a staircase structure including an inclined portion, and
the plurality of the electrode layers include at least a first electrode layer and a second electrode layer,
the staircase structure includes a plurality of contact plugs extending in the stacking direction,
and the plurality of contact plugs include at least a first contact plug and a second contact plug,
each of the plurality of the memory cell array layers includes a plurality of inner interconnection layers extending in a direction crossing the stacking direction, and
the plurality of inner interconnection layers include at least a first inner interconnection layer and a second inner interconnection layer,
the first inner connection layer connects the first contact plug and the first signal-line electrode,
the second inner interconnection layer connects the second contact plug and the second signal-line electrode,
the plurality of the electrode layers have a plurality of end portions corresponding one-to-one to the plurality of the electrode layers,
the plurality of end portions include at least a first end portion and a second end portion,
the first electrode layer includes the first end portion,
the second electrode layer includes the second end portion,
the first end portion is connected to the first contact plug,
the second end portion is connected to the second contact plug,
the first electrode layer is electrically connected to the first surface interconnection layer and the second surface interconnection layer via the first contact plug, the first inner interconnection layer, and the first signal-line electrode,
the second electrode layer is electrically connected to the first surface interconnection layer and the second surface interconnection layer via the second contact plug, the second inner interconnection layer, and the second signal-line electrode,
positions of the plurality of the end portions are displaced from each other for each stacked position in the staircase structure when viewed from a stacking direction of the multi-layered body,
the plurality of the memory cell array layers are stacked such that two memory cell array layers adjacent to each other in the stacking direction are connected to each other via the first surface interconnection layer and the second surface interconnection layer,
the two memory cell array layers adjacent to each other have a multi-layered boundary surface therebetween, and
the inclined portion of each of the two memory cell array layers adjacent to each other faces the multi-layered boundary surface.
The metes and bounds of the claimed limitation can not be determined for the following reasons: the claim recites “a plurality of memory cell array layers”, and in places, specifies requirements about “each” of the plurality of memory cell array layers (see e.g. the instances of “each” that have been bolded), but then refers back to limitations in an “each” phrase without using “each” again. Thus, all of the underlined limitations are unclear about whether they refer to “each” instance of the element in the entire device, or if it could only refer to one of them.
For example, the claim recites: “each of the plurality of the memory cell array layers includes a memory cell array region, a plurality of memory cells, a first surface interconnection layer, a second surface interconnection layer, and a plurality of signal-line electrodes” and then there are two limitations “the first surface interconnection layer is embedded in the first surface.” Because the underlined limitation refer back to “the first surface interconnection layer”, but does not use “each”, whereas the claim requires plural first surface interconnection layers, it is thus unclear if the claim requires that all first surface interconnections layers in the entire device are embedded in their respective first surfaces, or if the claim only requires that some, or one, of the first surface interconnection layers are embedded.
Claims 2-5 depend from claim 1 and inherit its deficiencies.
Furthermore, by reciting limitations that refer back to elements listed in “each” limitations, they cause further uncertainty. For example, claim 4 refers to “the multi-layered boundary surface”, which is in an “each limitation in claim 1. It is thus unclear if this limitation of claim 4 refers to all, some, or only one of the “multi-layered boundary surfaces”.
Claim Interpretation
The applicant is hereby notified that the examiner is treating claim 4 as a "product-by-process” claim. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” (See In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), and also see MPEP 2113).
The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. (See, e.g., In re Garnero, 412 F.2d 276, 279, 162 USPQ 221, 223 (CCPA 1979) and also see MPEP 2113).
Claim 4 recites the limitation “…the multi-layered boundary surface is a bonded surface, and the two memory cell array layers adjacent to each other are connected to each other at the bonded surface…”, which includes the result (being “connected” and “bonded”) of a process (bonding), despite being device a claim. The process of bonding results in two objects merely being connected together. Such connection could be achieved by many different processes, such as “direct” bonding, bonding using intermediate substances such as adhesives, or direct formation of a second material on a first material. Thus, the distinctive structural characteristic of this limitation is that there is a multi-layered boundary surface having two memory cell array layers adjacent to each other being connected, either directly or indirectly, at said surface.
Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. (See In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)).
Also note the use of 102/103 rejections for product-by-process claims has been approved by the courts. (See In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972), and also see MPEP 2113).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0261623 A1 (“Higashi”) in view of US 2020/0144242 A1 (“Park”).
Higashi teaches, for example:
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Applicant discloses:
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It is readily apparent from these two figures that Higashi teaches substantially the same invention as Applicant, with the exception that Applicant has flipped 200 vertically.
For example, 100 appears substantially identical in both figures and 300 appears substantially identical in both figures. Furthermore, in Higashi, 200 is substantially identical with 300, up to merely providing differences in numbering. Thus, the only difference between Higashi and the instant Application is that Applicant has inverted 200 vertically.
Higashi teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A semiconductor storage device (see e.g. Fig. 1) comprising:
a plurality of memory cell array layers stacked in a stacking direction (z-direction) of the semiconductor storage device,
wherein
each of the plurality of the memory cell array layers has a first surface and a second surface (see e.g. Sb1 and Sb2 in 300; see e.g. Sa1 and Sa2 in 200), the second surface is on an opposite side of the first surface,
each of the plurality of the memory cell array layers does not include a substrate (substrate 1 is only within 100),
each of the plurality of the memory cell array layers includes
a memory cell array region (see label in Fig. 1),
a plurality of memory cells,
a first surface interconnection layer (e.g. 39b in 300 or 39a in 200),
a second surface interconnection layer (e.g. 38b in 300 or 38a in 200), and
a plurality of signal-line electrodes (e.g. 37a or 37b),
the plurality of the memory cells are three-dimensionally in the memory cell array region (see e.g. Fig. 1),
the first surface interconnection layer is embedded in the first surface (see e.g. Fig. 1),
the second surface interconnection layer is embedded in the second surface (see e.g. Fig. 1),
the plurality of signal-line electrodes extend in the stacking direction (see e.g. Fig. 1),
the plurality of signal-line electrodes include at least a first signal-line electrode and a second signal-line electrode (see e.g. Fig. 1),
the plurality of signal-line electrode connect the first surface interconnection layer and the second surface interconnection layer (see e.g. Fig. 1),
each of the plurality of the memory cells includes a multi-layered body, the multi-layered body includes a plurality of insulating layers and a plurality of electrode layers (see e.g. Fig. 1),
the plurality of the insulating layers and the plurality of the electrode layers are alternately stacked one by one (see e.g. Fig. 1),
the multi-layered body has a staircase structure including an inclined portion (see e.g. Fig. 1), and
the plurality of the electrode layers include at least a first electrode layer and a second electrode layer (see e.g. Fig. 1),
the staircase structure includes a plurality of contact plugs (e.g. 30) extending in the stacking direction (see e.g. Fig. 1),
and the plurality of contact plugs include at least a first contact plug and a second contact plug (see e.g. Fig. 1),
each of the plurality of the memory cell array layers includes a plurality of inner interconnection layers (see e.g. 35, 36) extending in a direction crossing the stacking direction, and
the plurality of inner interconnection layers include at least a first inner interconnection layer and a second inner interconnection layer (see e.g. Fig. 1),
the first inner connection layer connects the first contact plug and the first signal-line electrode (see e.g. Fig. 1),
the second inner interconnection layer connects the second contact plug and the second signal-line electrode (see e.g. Fig. 1),
the plurality of the electrode layers have a plurality of end portions corresponding one-to-one to the plurality of the electrode layers (see e.g. Fig. 1),
the plurality of end portions include at least a first end portion and a second end portion (see e.g. Fig. 1),
the first electrode layer includes the first end portion, the second electrode layer includes the second end portion, the first end portion is connected to the first contact plug, the second end portion is connected to the second contact plug (see e.g. Fig. 1),
the first electrode layer is electrically connected to the first surface interconnection layer and the second surface interconnection layer via the first contact plug, the first inner interconnection layer, and the first signal-line electrode (see e.g. Fig. 1),
the second electrode layer is electrically connected to the first surface interconnection layer and the second surface interconnection layer via the second contact plug, the second inner interconnection layer, and the second signal-line electrode (see e.g. Fig. 1),
positions of the plurality of the end portions are displaced from each other for each stacked position in the staircase structure when viewed from a stacking direction of the multi-layered body (see e.g. Fig. 1),
the plurality of the memory cell array layers are stacked such that two memory cell array layers adjacent to each other in the stacking direction are connected to each other via the first surface interconnection layer and the second surface interconnection layer (see e.g. Fig. 1),
the two memory cell array layers adjacent to each other have a multi-layered boundary surface therebetween (see e.g. Fig. 1).
Higashi does not explicitly teach that the inclined portion of each of the two memory cell array layers adjacent to each other faces the multi-layered boundary surface (as noted above, Applicant has inverted 200 with respect to Higashi).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to invert 200 vertically with respect to Higashi, as such an orientation is well known in 3D memory devices.
For example, Park teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Higashi, that the inclined portion of each of the two memory cell array layers adjacent to each other faces the multi-layered boundary surface (see e.g. Fig. 10, reproduced below, wherein the include in S2 faces downward and the incline in S1 faces upward, each facing towards the interface between S1 and S2 where they are bonded).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Park, including the relative orientations of the staircase structures in S1 and S2, to the invention of Higashi. The motivation to do so is that the combination produces the predictable results of allowing the two cell regions to have “a structure that is identical or similar” to each other (para 91), thus having flexibility to change the cells slightly, using a stacking of various layers including peripheral circuitry and memory cells in various orientations (see e.g. Fig. 3), and to have a high integration density (para 92).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Higashi and Park together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
2. The semiconductor storage device according to claim 1, further comprising:
a control circuit layer (see Higashi, 100) comprising a circuit substrate (e.g. 1, see para 53), a control circuit (see para 53), and a circuit-side surface interconnection layer (see e.g. 41, 42),
the circuit substrate having a circuit-formed surface, the control circuit being on the circuit-formed surface, the circuit-side surface interconnection layer being on the circuit-formed surface and being electrically connected to the control circuit (see e.g. Fig. 1),
wherein the plurality of the memory cell array layers includes a first memory cell array layer stacked on the control circuit layer, the first surface interconnection layer is connected to the circuit-side surface interconnection layer (see e.g. Fig. 1).
3. The semiconductor storage device according to claim 1, further comprising:
a bit line (e.g. BL, see e.g. para 57);
a source line (e.g. SL, see e.g. para 55); and
a source-side interconnection layer at a position adjacent to the source line (see e.g. Fig. 1),
wherein each of the plurality of the memory cells includes a columnar part extending in the stacking direction, the columnar part has a first columnar-part end and a second columnar-part end, the second columnar-part end is on an opposite of the first columnar-part end, the bit line is electrically connected to the first columnar-part end, and the source line is electrically connected to the second columnar-part end (see e.g. Fig. 1).
4. The semiconductor storage device according to claim 1, wherein
the multi-layered boundary surface is a bonded surface (see e.g. para 18, 61-62, etc.), and the two memory cell array layers adjacent to each other are connected to each other at the bonded surface (see e.g. Fig. 1).
5. The semiconductor storage device according to claim 1, wherein the plurality of inner interconnection layers are closer to the multi-layered boundary surface than the plurality of the end portions of the plurality of the electrode layers (see e.g. Fig. 1; in combination, it would be obvious to face the inclines towards each other, or to face the inclines away from each other, thus providing the inner interconnections in their claimed orientation).
Higashi teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
US 2021/0134779 A1 (“Huang”) teaches 3D memory with inclined memory tiers facing each other (see cover figure).
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
Prosecution Insights