Prosecution Insights
Last updated: July 14, 2026
Application No. 18/182,780

SEMICONDUCTOR DEVICE HAVING CONTACT STRUCTURES FORMED IN THREE DIFFERENT INSULATING FILMS WITH DIFFERENT DIELECTRIC CONSTANT OR DIFFERENT YOUNG'S MODULUS FROM ONE ANOTHER

Final Rejection §103
Filed
Mar 13, 2023
Priority
Apr 30, 2009 — nonprovisional of PCTJP2009058510 +2 more
Examiner
MAI, ANH D
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Renesas Electronics Corporation
OA Round
4 (Final)
38%
Grant Probability
At Risk
5-6
OA Rounds
3m
Est. Remaining
48%
With Interview

Examiner Intelligence

Grants only 38% of cases
38%
Career Allowance Rate
265 granted / 701 resolved
-30.2% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
38 currently pending
Career history
758
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
82.8%
+42.8% vs TC avg
§102
11.6%
-28.4% vs TC avg
§112
5.0%
-35.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 701 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. Status of the Claims Species 1, as shown in FIG. 3, is elected. Amendment filed March 09, 2026 is acknowledged. Claims 1 and 23 have been amended. Claims 1-44 are pending. Action on merits of the Elected Species 1, claims 1-44 follows. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1-44 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over NOGUCHI et al. (US. Pub. No. 2004/0227242) in view of HOTTA et al. (US. Pub. No. 2007/0020829) both of record. With respect to claim 1, NOGUCHI teaches a semiconductor device substantially as claimed including: a semiconductor substrate (1); a MISFET (9) formed on the semiconductor substrate (1); 5a contact interlayer insulating film (11) covering the MISFET (9) formed on the semiconductor substrate (1); a first plug (13) formed in the contact interlayer insulating film (11) and electrically connected to the MISFET (9); a first interlayer insulating film (15) formed on the contact 10interlayer insulating film (11); a first layer wiring (20) formed in the first interlayer insulating film (15) and electrically connected to the first plug (13); a barrier insulating film formed on the first interlayer insulating film (15) and the first layer wiring (20), the barrier insulating film formed of i) a SiCN film (21) and ii) a SiC film (22) formed on the SiCN film (21); a second interlayer insulating film (23/25) formed on the barrier insulating film (21/22) such that the second interlayer insulating film directly contact the barrier insulating film (21/22); 15a second plug (34 plug) formed in the second interlayer insulating film (23/25) and electrically connected to the first layer wiring (20); and a second layer wiring (34 wiring) formed in the second interlayer insulating film (23/25) and electrically connected to the second plug (34 plug), wherein the contact interlayer insulating film (11) is formed of 20a high-dielectric-constant film having the highest dielectric constant among the contact interlayer insulating film (11), the first interlayer insulating film (15) and the second interlayer insulating film (23/25), wherein the second interlayer insulating film (23/25) is formed of a 25low-dielectric-constant film having the lowest dielectric constant among the contact interlayer insulating film (11), the first interlayer insulating film (15) and the second interlayer insulating film (23/25), and - 108 -wherein the first interlayer insulating film (15) is formed of a middle-dielectric-constant film (15) having dielectric constant lower than that of the contact interlayer insulating film (11) and higher than that of the second interlayer insulating film (23/25), wherein a dielectric constant of the high-dielectric-constant film (11, TEOS) is larger than or equal to 3.5, wherein a dielectric constant of the middle-dielectric-constant film (15) is larger than or equal to 2.8 and smaller than 3.5, and wherein a dielectric constant of the low-dielectric-constant film (23/25) is smaller than 2.8. (See FIG. 13). Thus, NOGUCHI is shown to teach all the features of the claim with the exception of explicitly disclosing the barrier insulating film being formed of a SiCO film on the SiCN film. However, HOTTA teaches a semiconductor device including: a barrier insulating film formed on a first interlayer insulating film (17) and a first layer wiring (19), the barrier insulating film formed of i) a SiCN film (21) and ii) a SiCO film (22) formed on the SiCN film (21). (See FIG. 3, [0064]). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form 5the barrier insulating film of NOGUCHI utilizing the SiCO film formed on the SiCN film as taught by HOTTA to prevent diffusion of amine compound from the SiCN into the interlayer insulating film thereover. Moreover, given a finite number of materials and their compounds, it is obvious to try without undue experimentation. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416. With respect to claim - 115 -23, NOGUCHI teaches a semiconductor device substantially as claimed including: a semiconductor substrate (1); a MISFET (9) formed on the semiconductor substrate (1); a contact interlayer insulating film (11) covering the MISFET (9) formed 5on the semiconductor substrate (1); a first plug (13) formed in the contact interlayer insulating film (11) and electrically connected to the MISFET (9); a first interlayer insulating film (15) formed on the contact interlayer insulating film; 10a first layer wiring (20) formed in the first interlayer insulating film (15) and electrically connected to the first plug (13); a barrier insulating film (21/22) formed on the first interlayer insulating film (15) and the first layer wiring (20), the barrier insulating film being formed of i) a SiCN film (21) and ii) a SiC film (22) formed on the SiCN film (21); a second interlayer insulating film (23/25) formed on the barrier insulating film (21/22) such that the second interlayer insulating film directly contact the barrier insulating film (21/22); a second plug (34 plug) formed in the second interlayer insulating film (23/25) 15and electrically connected to the first layer wiring (20); and a second layer wiring (34 wiring) formed in the second interlayer insulating film (23/25) and electrically connected to the second plug (31), wherein the contact interlayer insulating film (11) is formed of a high-Young's-modulus film (TEOS) having the highest Young's modulus among 20the contact interlayer insulating film (11), the first interlayer insulating film (15) and the second interlayer insulating film (23/25), wherein the second interlayer insulating film (23/25) is formed of a low-Young's-modulus film having the lowest Young's modulus among the contact interlayer insulating film (11), the first interlayer 25insulating film (15) and the second interlayer insulating film (23/25), and wherein the first interlayer insulating film (15) is formed of a middle-Young's-modulus film having Young's modulus lower than that - 116 -of the contact interlayer insulating film (11) and higher than that of the second interlayer insulating film (23/25), wherein a Young's modulus of the high-Young's-modulus film (11, TEOS) is larger than or equal to 30, wherein a Young's modulus of the middle-Young's-modulus film (15, MSQ, HSQ) larger than or equal to 15 and smaller than 30, and wherein a Young's modulus of the low-Young's-modulus film (23/25, porous MSQ, HSQ) is smaller than 15. (See FIG. 13). Note that, the Young's modulus or the hardness of a material is directly related to or the characteristics of, that material. Thus, NOGUCHI is shown to teach all the features of the claim with the exception of explicitly disclosing the barrier insulating film being formed of a SiCO film on the SiCN film. However, HOTTA teaches a semiconductor device including: a barrier insulating film formed on a first interlayer insulating film (17) and first layer wiring (19), the barrier insulating film being formed of i) a SiCN film (21) and ii) a SiCO film (22) formed on the SiCN film (21). (See FIG. 3, [0064]). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form 5the barrier insulating film of NOGUCHI being formed of the SiCO film formed on the SiCN film as taught by HOTTA to prevent diffusion of amine compound from the SiCN into the interlayer insulating film thereover. Moreover, given a finite number of materials and their compounds, it is obvious to try without undue experimentation. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416. With respect to claims 2 and 24, the high-dielectric-constant film (11) of NOGUCHI or HOTTA, is formed of either of a silicon oxide film, a SiOF film or a TEOS film, wherein the first interlayer insulating film (15) is formed of 10either of a SiOC film, an HSQ film, or an MSQ film, and wherein the second interlayer insulating film (23/25) is formed of either of a SiOC film having a void, an HSQ film having a void, or an MSQ film having a void. With respect to claims 325 and 25, the semiconductor device of NOGUCHI further comprises a damage protection film (35) formed on the second interlayer insulating film (23/25), - 109 -wherein the damage protection film (35) is formed of a SiOC film, and wherein the second layer wiring (34 wiring) and the second plug (34 plug) are formed to be buried in the second interlayer insulating film (23/25) and the damage 5protection film (35). With respect to claims 4 and 26, in view of HOTTA, a thickness of the first interlayer insulating film (1) is larger than or equal to 100 nm. With respect to claims 5 and 27, in view of HOTTA, a thickness of the first interlayer insulating film (17) is smaller than or equal to 200 nm. With respect to claims 6 and 28, in view of HOTTA, a thickness of the first interlayer insulating film (17) is smaller than or equal to 200 nm. With respect to claims 7 and 29, in view of HOTTA, a thickness of the first interlayer insulating film (17) is larger than or equal to 100 nm. With respect to claims 8 and 30, in view of HOTTA, a thickness of the first interlayer insulating film (17) is smaller than or equal to 200 nm. With respect to claims 9 and 31, in view of HOTTA, a thickness of the first interlayer insulating film (17) is smaller than or equal to 200 nm. With respect to claims 10 and 32, in view of HOTTA, a thickness of the second interlayer insulating film (23) is 200 nm to 2000 nm. With respect to claims 11 and 33, in view of HOTTA, a thickness of the second interlayer insulating film (23) is 200 nm to 2000 nm. With respect to claims 12 and 34, the high-dielectric-constant film (11) of NOGUCHI or HOTTA, is formed of a TEOS film. With respect to claims 13 and 35, the high-dielectric-constant film (11) of NOGUCHI or HOTTA, is formed of the TEOS film. With respect to claims 14 and 36, the semiconductor device of NOGUCHI further comprises: a third interlayer insulating film (37/39) formed on the second interlayer insulating film (23/25); 5a third plug (44 plug) formed in the third interlayer insulating film (37/39); and a third layer wiring (44 wiring) formed in the third interlayer insulating film (37/39) and electrically connected to the third plug (44 plug), wherein the third interlayer insulating film (37/39) is formed of 10either of a SiOC film, an HSQ film, or an MSQ film. (See FIG. 16). With respect to claims 15 and 37, in view of HOTTA, the semiconductor device further comprising: a fourth interlayer insulating film (45) formed on the third interlayer insulating film (35); a fourth plug (54 plug) formed in the fourth interlayer insulating film (45); a fourth layer wiring (45 wiring) formed on the fourth interlayer insulating film (45) and electrically connected to the fourth plug (45 plug); and a passivation film (56) formed on the fourth layer wiring (54 wiring), wherein the fourth layer wiring (54 wiring) is exposed from an opening portion formed to the passivation film (56), and wherein the fourth interlayer insulating film (45) is formed of either of a silicon oxide film, a SiOF film or a TEOS film. (See FIGs. 21, 23). With respect to claims 16 and 38, the semiconductor device of NOGUCHI further comprises: a third interlayer insulating film (37/39) formed on the second interlayer insulating film (23/25); 5a third plug (44 plug) formed in the third interlayer insulating film (37/39); and a third layer wiring (44 wiring) formed in the third interlayer insulating film (37/39) and electrically connected to the third plug (44 plug), wherein the third interlayer insulating film (37/39) is formed of 10either of a SiOC film, an HSQ film, or an MSQ film. (See FIG. 16). With respect to claims 17 and 39, in view of HOTTA, the semiconductor device further comprising: a fourth interlayer insulating film (45) formed on the third interlayer insulating film (35); a fourth plug (54 plug) formed in the fourth interlayer insulating film (45); a fourth layer wiring (45 wiring) formed on the fourth interlayer insulating film (45) and electrically connected to the fourth plug (45 plug); and a passivation film (56) formed on the fourth layer wiring (54 wiring), wherein the fourth layer wiring (54 wiring) is exposed from an opening portion formed to the passivation film (56), and wherein the fourth interlayer insulating film (45) is formed of either of a silicon oxide film, a SiOF film or a TEOS film. (See FIGs. 21, 23). With respect to claims 18 and 40, the semiconductor device of NOGUCHI further comprises: a third interlayer insulating film (37/39) formed on the second interlayer insulating film (23/25); 5a third plug (44 plug) formed in the third interlayer insulating film (37/39); and a third layer wiring (44 wiring) formed in the third interlayer insulating film (37/39) and electrically connected to the third plug (44 plug), wherein the third interlayer insulating film (37/39) is formed of 10either of a SiOC film, an HSQ film, or an MSQ film. (See FIG. 16). With respect to claims 19 and 41, in view of HOTTA, the semiconductor device further comprising: a fourth interlayer insulating film (45) formed on the third interlayer insulating film (35); a fourth plug (54 plug) formed in the fourth interlayer insulating film (45); a fourth layer wiring (45 wiring) formed on the fourth interlayer insulating film (45) and electrically connected to the fourth plug (45 plug); and a passivation film (56) formed on the fourth layer wiring (54 wiring), wherein the fourth layer wiring (54 wiring) is exposed from an opening portion formed to the passivation film (56), and wherein the fourth interlayer insulating film (45) is formed of either of a silicon oxide film, a SiOF film or a TEOS film. (See FIGs. 21, 23). With respect to claims 20 and 42, in view of HOTTA, the semiconductor device further comprising: a fourth interlayer insulating film (45) formed on the second interlayer insulating film (23); a fourth plug (54 plug) formed in the fourth interlayer insulating film (45); a fourth layer wiring (45 wiring) formed on the fourth interlayer insulating film (45) and electrically connected to the fourth plug (45 plug); and a passivation film (56) formed on the fourth layer wiring (54 wiring), wherein the fourth layer wiring (54 wiring) is exposed from an opening portion formed to the passivation film (56), and wherein the fourth interlayer insulating film (45) is formed of either of a silicon oxide film, a SiOF film or a TEOS film. (See FIGs. 21, 23). With respect to claims 21 and 43, in view of HOTTA, the semiconductor device further comprising: a fourth interlayer insulating film (45) formed on the second interlayer insulating film (23); a fourth plug (54 plug) formed in the fourth interlayer insulating film (45); a fourth layer wiring (45 wiring) formed on the fourth interlayer insulating film (45) and electrically connected to the fourth plug (45 plug); and a passivation film (56) formed on the fourth layer wiring (54 wiring), wherein the fourth layer wiring (54 wiring) is exposed from an opening portion formed to the passivation film (56), and wherein the fourth interlayer insulating film (45) is formed of either of a silicon oxide film, a SiOF film or a TEOS film. (See FIGs. 21, 23). With respect to claims 22 and 44, in view of HOTTA, the semiconductor device further comprising: a fourth interlayer insulating film (45) formed on the second interlayer insulating film (23); a fourth plug (54 plug) formed in the fourth interlayer insulating film (45); a fourth layer wiring (45 wiring) formed on the fourth interlayer insulating film (45) and electrically connected to the fourth plug (45 plug); and a passivation film (56) formed on the fourth layer wiring (54 wiring), wherein the fourth layer wiring (54 wiring) is exposed from an opening portion formed to the passivation film (56), and wherein the fourth interlayer insulating film (45) is formed of either of a silicon oxide film, a SiOF film or a TEOS film. (See FIGs. 21, 23). Response to Arguments Applicant's arguments filed March 09, 2026 have been fully considered but they are not persuasive. Applicant argues: Applicant respectfully submits that the cited references, taken individually or in combination, fail to disclose or suggest the features of "a first interlayer insulating film formed of a middle-dielectric-constant film having a dielectric constant larger than or equal to 2.8 and smaller than 3.5" and "a second interlayer insulating film formed of a low-dielectric-constant film having a dielectric constant smaller than 2.8," wherein the dielectric constant of the first interlayer insulating film is higher than that of the second interlayer insulating film. However, NOGUCHI explicitly teaches that the first interlayer insulating film (15) comprises material such as PAE (dielectric constant of 2.8) or p-MTES (dielectric constant of 3.2). Thus, the limitation of “middle-dielectric-constant film a dielectric constant larger than or equal to 2.8 and smaller than 3.5” is met. Further, the second interlayer insulating film (23) of NOGUCHI can utilize low-dielectric-constant material such as MSQ, HSQ including their porous materials, hence, dielectric constant is smaller than 2.8. Thus, the limitation of “low-dielectric-constant film having a dielectric constant larger smaller than 2.8” is met. Regarding the barrier insulating film, Applicant asserts: Noguchi teaches that the upper barrier insulating film (element 22) is a SiC film that does "not include nitrogen (N) or oxygen (O)." (See Noguchi, paragraphs [0103] and [0109]). Applicant, apparently, cannot tell the difference between “not contain nitrogen and carbon” (paragraph [0103]) and “not contain nitrogen and oxygen”, applicant’s assertion. Paragraph [0109], NOGUCHI discusses about the material for the second interlayer dielectric film 23, not barrier film 22. In view of HOTTA, SiCO is used for the upper layer 22 of the barrier insulating film. According to HOTTA, SiCO, film 22, is used to prevent diffusion of amine compound from the lower barrier layer 21, SiCN, into the second interlayer insulating film 23. (See paragraph [0064]). The limitations are met. The rejection of all claims is maintained. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached on 8:00-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A. Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH D MAI/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 2 earlier events
May 12, 2025
Response Filed
Aug 26, 2025
Final Rejection mailed — §103
Oct 22, 2025
Response after Non-Final Action
Nov 25, 2025
Request for Continued Examination
Dec 03, 2025
Response after Non-Final Action
Dec 08, 2025
Non-Final Rejection mailed — §103
Mar 09, 2026
Response Filed
May 12, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
38%
Grant Probability
48%
With Interview (+9.9%)
3y 8m (~3m remaining)
Median Time to Grant
High
PTA Risk
Based on 701 resolved cases by this examiner. Grant probability derived from career allowance rate.

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