CTNF 18/182,879 CTNF 78034 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 3-16 and 18-20 are rejected under 35 U.S.C. 102 ( a)(1 ) as being anticipated by Gallagher et al (US 5,948,533; hereinafter Gallagher) . Regarding claim 1, Gallagher discloses an integrated circuit (IC) package substrate (see figure 1) comprising: a glass substrate (55); a via extending between first and second surfaces of the glass substrate (see figure 3); and a conductive material (70,85,80) provided in the via (see figure 3), the conductive material including gallium and silver (column 5 lines 60- column 6 line 16; column 6 line 44-48 (Ga); column 7 lines 31-36 (Silver) and column 8 lines 16-25). Regarding claim 3, Gallagher discloses the integrated circuit (IC) package substrate (see figure 1), further including a filler material (column 6 line 3-8 and column 7 lines 38-column 8 line 25) in the conductive material (column 7 line 31-36 and column 8 lines 16-25). Regarding claim 4, Gallagher discloses the integrated circuit (IC) package substrate (see figure 1), wherein the filler material has a negative coefficient of thermal expansion (column 6 line 3-8 and column 7 lines 38-column 8 line 25). Regarding claim 5 Gallagher discloses the integrated circuit (IC) package substrate (see figure 1), wherein the conductive material includes at least one of indium, tin, or zinc (column 7 line 31-36 and column 8 lines 16-25). Regarding claim 6, Gallagher discloses the integrated circuit (IC) package substrate (see figure 1), wherein the conductive material includes copper (column 7 line 31-36 and column 8 lines 16-25). Regarding claim 7, Gallagher discloses the integrated circuit (IC) package substrate (see figure 1), wherein the filler material includes a carbon nano tube (column 6 line 3-8 and column 7 lines 38-column 8 line 25). Regarding claim 8, Gallagher discloses the integrated circuit (IC) package substrate (see figure 1), wherein the filler material includes a ceramic filler (column 6 line 3-8 and column 7 line 38-column 8 line 25). Regarding claim 9, Gallagher discloses the integrated circuit (IC) package substrate (see figure 1), wherein the filler material includes a diamond particle (column 6 line 3-8 and column 7 lines 38-column 8 line 25). Regarding claim 10, Gallagher discloses the integrated circuit (IC) package substrate (see figure 1), wherein the conductive material (column 5 lines 60- column 6 line 16; column 6 line 44-48 (Ga); column 7 lines 31-36 (Silver) and column 8 lines 16-25) includes a first metal material, the filler material including a second metal material different from the first metal material (column 6 line 4-6 and column 8 lines 3-25). Regarding claim 11, Gallagher discloses an integrated circuit (IC) package substrate (see figure 1), further including an adhesive layer (column 8 lines 28-33) provided in the via, the adhesive layer to coat an inner surface of the via. Regarding claim 12, Gallagher discloses an integrated circuit (IC) package substrate (see figure 1), wherein the adhesive layer includes silicon and hydrogen (column 8 lines 28-33). Regarding claim 13, Gallagher discloses an integrated circuit (IC) package substrate (see figure 1), wherein the filler material particle (column 6 line 3-8 and column 7 line 38-column 8 line 25) is between 1 percent volume and 30 percent volume of the conductive material. Regarding claim 14, Gallagher discloses an integrated circuit (IC) package substrate (see figure 1), wherein the conductive material (column 7 lines 31-36) has a first coefficient of thermal expansion, the filler material particle (column 6 line 4-6 and column 7 line 38-column 8 line 25) has a second coefficient of thermal expansion, the first coefficient of thermal expansion greater than the second coefficient of thermal expansion. Regarding claim 15, Gallagher discloses an integrated circuit (IC) package substrate (see figure 1), wherein the first coefficient of thermal expansion (column 7 lines 31-36) is greater than zero and wherein the second coefficient of thermal expansion ( is less than zero. Regarding claim 16, Gallagher discloses a glass core of an integrated circuit (IC) package substrate (see figure 1), the glass core (55) comprising: a first surface; a second surface opposite the first surface (see figure 3); and a conductive pillar (70,80,85) extending between the first and second surfaces, the conductive pillar including gallium and silver (column 5 lines 60- column 6 line 7; column 7 line 44-48 (Ga) and column 7 lines 31-36 (Silver). Regarding claim 18, Gallagher discloses a glass core of an integrated circuit (IC) package substrate (see figure 1), wherein the conductive pillar further includes a material having a negative coefficient of thermal expansion (column 6 line 4-6 and column 7 line 38-column 8 line 25). Regarding claim 19, Gallagher discloses a method to produce a glass core for a package substrate of an integrated circuit chip (see figure 1), the method comprising: providing a via (see figure 3) extending between first and second surfaces of the glass core (55); and providing a conductive material (70, 80, 85) in the via, the conductive material including a gallium and silver (column 5 lines 60- column 6 line 7; column 7 line 44-48 (Ga) and column 7 lines 31-36 (Silver). Regarding claim 20 Gallagher discloses the method (see figure 1), wherein the conductive material (70, 80, 85) further includes a filler material, and wherein providing the conductive material in the via includes: depositing a metallic paste in the via, the metallic paste in including the filler material; and applying heat to solidify the metallic paste (column 6 line 3-8 and column 7 lines 38-column 8 line 25) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 2 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gallagher et al (US 5,948,533; hereinafter Gallagher) in view Kajihara (US 8,431,833) . Regarding claim 2, Gallagher discloses the claimed invention except for the via is hourglass shaped or cylindrical. Kajihara teaches a substrate (1) comprising: a glass layer (10); a via (13a) penetrating through the glass layer (see figure 1d); the via (13a) being a hourglass shape or cylindrical (see figure 1d). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make Gallagher’s via having an hourglass or cylindrical shape as taught by Kajihara to provide the via with a shape that will avoid the occurrence of voids or the like when filling via with the conductive material. Regarding claim 17, Gallagher discloses the claimed invention except for a diameter of the conductive pillar decreases from the first surface to a point between the first and second surfaces, the diameter of the conductive pillar to increase from the point to the second surface. Kajihara teaches a substrate (1) comprising: a glass layer (10); a conductive pillar (13) extending between the first and second surfaces, a diameter of the conductive pillar (13) decreases from the first surface to a point between the first and second surfaces and the diameter of the conductive pillar to increase from the point to the second surface (see figure 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make Gallagher’s conductive pillar having a diameter that decreases from the first surface to a point between the first and second surfaces and increase from the point to the second surface as taught by Kajihara to provide a conductive pillar with a shape that will improve electrical signal reliability and thermal management . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Matsui et al (US 9,578,738), Baek et al (US 10,347,598), Min et al (US 12,526,930 and US 11,737,211), Bae et al (US 12,284,758), Kim et al (US 10,347,613) and Che et al (US 12,322,669) disclose an integrated circuit package substrate . 07-100 AIA 5. Any inquiry concerning this communication should be directed to Angel R. Estrada at telephone number (571) 272-1973. The Examiner can normally be reached on Monday-Friday (8:30am -5:00pm) . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N. Hayman can be reached on (571) 270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) OR 571-272-1000. May 5, 2026 /ANGEL R ESTRADA/Primary Examiner, Art Unit 2841 Application/Control Number: 18/182,879 Page 2 Art Unit: 2841 Application/Control Number: 18/182,879 Page 3 Art Unit: 2841 Application/Control Number: 18/182,879 Page 4 Art Unit: 2841 Application/Control Number: 18/182,879 Page 5 Art Unit: 2841 Application/Control Number: 18/182,879 Page 6 Art Unit: 2841 Application/Control Number: 18/182,879 Page 7 Art Unit: 2841 Application/Control Number: 18/182,879 Page 8 Art Unit: 2841
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