DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Election/Restrictions
3. Applicant’s election without traverse of Invention II, identified as encompassing claims 15-34 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 15-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0266059 A1), hereinafter as L1, in view of Young et al. (KR 20190055992 A, see attached translation document), hereinafter as Y1
5. Regarding Claim 15, L1 discloses a method (see in particular Figs. 1, 7A-11B) comprising:
forming a 2-D material channel layer (element 15, see [0021] “first metal dichalcogenide film 15” and [0019] “the 2D material is a metal dichalcogenide”) over a substrate (element 10, see [0021] “substrate 10”);
forming a 2-D material charge storage layer (element 25, see [0021] “second metal dichalcogenide film 25”; note, the material and structure as taught by the prior art are the same as claimed such that the layer would function as a charge storage layer during operation in the same manner) over the 2-D material channel layer (see Fig. 1B);
forming a patterned mask having openings exposing the 2-D material charge storage layer (see [0041] “Using photolithographic and etching operations the first and second metal dichalcogenide films 15, 25 are patterned to form a channel region 50, as shown in FIGS. 8A and 8B” and [0042] “Using the oxygen plasma etching operations of the present disclosure, contact window openings 20 are formed in the second metal dichalcogenide film 15 exposing the first metal dichalcogenide film 15, as shown in FIGS. 9A and 9B”;
Note, the photolithographic and etching operations using oxygen plasma etching inherently involves a patterned mask in order for the removal of the element 25 to form selective openings of element 20);
removing portions of the 2-D material charge storage layer (see [0041-0042] and Fig. 9B) by using the patterned mask as an etch mask (see [0041-0042] and Fig. 9B);
forming source/drain contacts (see Figs. 11A-B elements 35, see [0021] “Source/drain electrodes 35”);
removing the patterned mask (see Figs. 1A-B, 11B the patterned mask is not part of the final device structure and is removed); and
forming a gate structure (element 45, see [0021] “A gate electrode 45 is formed on top of the dielectric layer 40”) over the 2-D material channel layer and between the source/drain contacts (see Figs. 1A-B).
L1 does not explicitly disclose forming source/drain contacts in the openings of the patterned mask.
Y1 discloses forming a patterned mask having openings, forming source/drain contacts in the openings of the patterned mask (see Fig. 2 and pg. 6 “A shadow mask is disposed on the substrate
coated with the photoresist, and UV is irradiated. Subsequently, a source electrode and a drain electrode are formed on the UV-irradiated substrate by an evaporation method. Then, a region where the photoresist is formed is removed using a lift-off process.”).
The patterned mask used for forming the source/drain contacts as taught by Y1 is incorporated as the patterned mask for forming the source/drain contacts of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known method of forming source/drain contacts for another in a similar device for which alternative methods are provided as selectable to obtain predictable results (see pg. 6 “Specifically, a source electrode and a drain electrode can be formed using a shadow mask or photolithography”).
6. Regarding Claim 16, L1, Y1 disclose the method of claim 15, wherein the 2-D material channel layer and the 2-D material charge storage layer comprise the same chalcogen atoms (see [0023] “the first and second metal dichalcogenide films are transition metal dichalcogenide films that are different from each other in composition and are selected from the group consisting of MoS2, WS2, MoSe2, WSe2, MoTe2, and WTe2” Selected as MoS2 and WS2 which have the same chalcogen atoms of sulfur).
7. Regarding Claim 18, L1, Y1 disclose the method of claim 15, wherein after removing portions of the 2-D material charge storage layer, the 2-D material channel layer is exposed by the openings (see L1 Fig. 9B element 15 is exposed after removing portions of element 25).
8. Regarding Claim 19, L1, Y1 disclose the method of claim 15, wherein the source/drain contacts are formed over the 2-D material channel layer (see Figs. 11A-B elements 35, see [0021] “Source/drain electrodes 35”).
9. Regarding Claim 20, L1, Y1 disclose the method of claim 15, wherein band gaps of the 2-D material channel layer and the 2-D material charge storage layer are both in a range from about 1 eV to about 3 eV (see L1 [0023] “the first and second metal dichalcogenide films are transition metal dichalcogenide films that are different from each other in composition and are selected from the group consisting of MoS2, WS2, MoSe2, WSe2, MoTe2, and WTe2” The material are the same as those provided by the Applicant’s invention which have the same material properties including the band gaps).
10. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0266059 A1), hereinafter as L1, in view of Young et al. (KR 20190055992 A, see attached translation document), hereinafter as Y1, in view of Yeom et al. (US 2019/0044009 A1), hereinafter as Y2
11. Regarding Claim 17, L1, Y1 disclose the method of claim 15.
L1, Y1 do not disclose wherein removing portions of the 2-D material charge storage layer is performed by using an atomic layer etching process.
Y2 discloses wherein removing portions of the 2-D material charge storage layer is performed by using an atomic layer etching process (see [0084] “ALE process may be etching using plasma” and [0013] 2-D material can include molybdenum or tungsten with chalcogen of selenium or sulfur).
The atomic layer etching process as taught by Y2 is incorporated as an atomic etching process of L1,Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y2 with L1,Y1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known method of etching 2-D material for another to obtain predictable results (see Y2 [0084]).
12. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0266059 A1), hereinafter as L1, in view of Young et al. (KR 20190055992 A, see attached translation document), hereinafter as Y1, in view of Huang et al. (US 2021/0018780 A1), hereinafter as H1
13. Regarding Claim 21, L1, Y1 disclose the method of claim 15, further comprising patterning the 2-D material channel (see L1 Fig. 7B-8B and [0041] “The photolithographic and etching operations expose the substrate 10 surrounding the patterned first and second metal dichalcogenide films 15, 25”).
L1, Y1 do not disclose patterning the 2-D material channel layer after forming the source/drain contacts and prior to forming the gate structure.
H1 discloses patterning the 2-D material channel layer after forming the source/drain contacts and prior to forming the gate structure (see in particular Figs. 3A-D the 2-D material channel layer element 110 is patterned after the source/drain contacts elements 120 are formed and prior to forming the gate structure element 150, see [0020] “active layer 110 may be a 2D semiconductor active layer formed from a transition metal dichalcogenide (TMD) … source electrode 120”).
The order of patterning the 2-D material channel layer as taught by H1 is incorporated as the order of patterning the 2-D material channel layer of L1, Y1 (see L1 the step between Figs. 7B-8B is changed to be after Fig. 11B).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known order of patterning the 2-D channel layer for another in a similar device to obtain predictable results (see H1 Figs. 3A-D).
14. Claims 22-28 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0266059 A1), hereinafter as L1, in view of Lin et al. (US 2016/0379901 A1), hereinafter as L2
15. Regarding Claim 22, L1 discloses a method (see in particular Figs. 1, 7A-11B) comprising:
transferring a 2-D material channel (element 15, see [0021] “first metal dichalcogenide film 15” and [0019] “the 2D material is a metal dichalcogenide”) over a substrate (element 10, see [0021] “substrate 10”);
transferring a 2-D material charge storage (element 25, see [0021] “second metal dichalcogenide film 25”; note, the material and structure as taught by the prior art are the same as claimed such that the layer would function as a charge storage layer during operation in the same manner) over the 2-D material (see Fig. 1B);
patterning the 2-D material charge storage to form source/drain openings in the 2-D material charge storage (see [0041] “Using photolithographic and etching operations the first and second metal dichalcogenide films 15, 25 are patterned to form a channel region 50, as shown in FIGS. 8A and 8B” and [0042] “Using the oxygen plasma etching operations of the present disclosure, contact window openings 20 are formed in the second metal dichalcogenide film 15 exposing the first metal dichalcogenide film 15, as shown in FIGS. 9A and 9B”;
Note, the photolithographic and etching operations using oxygen plasma etching inherently involves a patterned mask in order for the removal of the element 25 to form selective openings of element 20);
forming source/drain contacts (see Figs. 11A-B elements 35, see [0021] “Source/drain electrodes 35”) over the 2-D material channel and in the source/drain openings, respectively (see Fig. 11B);
depositing a gate dielectric layer (element 40, see [0021] “gate dielectric layer 40”) to cover the source/drain contacts and the 2-D material charge storage (see Fig. 1B); and
forming a gate structure (element 45, see [0021] “A gate electrode 45 is formed on top of the dielectric layer 40”) over the gate dielectric layer and directly over the 2-D material charge storage (see Fig. 1B).
L1 does not explicitly disclose the channel is a stack; the charge storage is a stack.
L2 discloses the channel is a stack; the charge storage is a stack (see Fig. 1 and [0015] “the first 2D material sub-layer 104-1 of the first conductive layer 104 may comprise MoS2, MoSe2, WS2, WSe2, combinations thereof, or the like. The second 2D material sub-layer 104-2 of the first conductive layer 104 may also comprise MoS2, MoSe2, WS2, WSe2, combinations thereof, or the like.” Selected as a combination of material for each of the two layers).
The stack for the channel and charge storage respectively as taught by L2 is incorporated as a stack for the channel and charge storage respectively of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L2 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known number of layers in 2-D material channel and charge storage layers for another for which the two options are provided as selectable alternatives in a similar device to obtain predictable results (see L1 [0015]).
16. Regarding Claim 23, L1, L2 disclose the method of claim 22, wherein the source/drain openings expose the 2-D material channel stack (see L1 Fig. 9B).
17. Regarding Claim 24, L1, L2 disclose the method of claim 22, wherein the 2-D material charge storage stack comprises a plurality of 2-D material charge storage layers, wherein at least two of the 2-D material charge storage layers comprise different materials having a band gap difference lower than about 0.5 eV (see L1 [0023] and L2 [0015] The material are the same as those provided by the Applicant’s invention which have the same material properties including the band gaps).
18. Regarding Claim 25, L1, L2 disclose the method of claim 24, wherein the at least two of the 2-D material charge storage layers comprise same chalcogen atoms and different transition metals (see L2 [0015] MoS2 and WS2).
19. Regarding Claim 26, L1, L2 disclose the method of claim 22, wherein the 2-D material channel stack comprises a plurality of 2-D material channel layers, wherein at least two of the 2-D channel layers comprise different materials having a band gap difference lower than about 0.5 eV (see L1 [0023] and L2 [0015] The material are the same as those provided by the Applicant’s invention which have the same material properties including the band gaps).
20. Regarding Claim 27, L1, L2 disclose the method of claim 26, wherein the at least two of the 2-D material channel layers comprise same chalcogen atoms and different transition metals (see L2 [0015] MoS2 and WS2).
21. Regarding Claim 28, L1, L2 disclose the method of claim 22, wherein the 2-D material charge storage stack comprises n layers of 2-D material charge storage layers, the 2-D material channel stack comprises m layers of 2-D material channel layers, and n is greater than m (see L2 [0015]).
22. Claims 29-31 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0266059 A1), hereinafter as L1, in view of in view of Huang et al. (US 2021/0018780 A1), hereinafter as H1
23. Regarding Claim 29, L1 discloses a method (see in particular Figs. 1, 7A-11B) comprising:
providing a semiconductor structure (see [0021] “semiconductor device 100”) comprising:
a substrate (element 10, see [0021] “substrate 10”);
a first 2-D material channel layer (element 15, see [0021] “first metal dichalcogenide film 15” and [0019] “the 2D material is a metal dichalcogenide”) over the substrate (see Fig. 1B); and
a first 2-D material charge storage layer (element 25, see [0021] “second metal dichalcogenide film 25”; note, the material and structure as taught by the prior art are the same as claimed such that the layer would function as a charge storage layer during operation in the same manner) over the first 2-D material channel layer (see Fig. 1B);
performing a first etching process to pattern the first 2-D material charge storage layer (see [0041] “Using photolithographic and etching operations the first and second metal dichalcogenide films 15, 25 are patterned to form a channel region 50, as shown in FIGS. 8A and 8B” and [0042] “Using the oxygen plasma etching operations of the present disclosure, contact window openings 20 are formed in the second metal dichalcogenide film 15 exposing the first metal dichalcogenide film 15, as shown in FIGS. 9A and 9B”;
Note, the photolithographic and etching operations using oxygen plasma etching inherently involves a patterned mask in order for the removal of the element 25 to form selective openings of element 20);
forming source/drain contacts (see Figs. 11A-B elements 35, see [0021] “Source/drain electrodes 35”) on opposite sides (left and right sides) of the patterned first 2-D material charge storage layer (see Figs. 11A-B);
performing a second etching process to pattern the first 2-D material channel layer (see [0041-0042] and Fig. 9B), such that the source/drain contacts and the patterned first 2-D material charge storage layer are over the patterned first 2-D material channel layer (see Fig. 1B);
depositing a gate dielectric layer (element 40, see [0021] “gate dielectric layer 40”) to cover the source/drain contacts and the patterned first 2-D material charge storage layer (see Fig. 1B); and
forming a gate structure (element 45, see [0021] “A gate electrode 45 is formed on top of the dielectric layer 40”) over the gate dielectric layer and between the source/drain contacts (see Fig. 1B).
L1 does not disclose after forming the source/drain contacts, performing a second etching process to pattern the first 2-D material channel layer.
H1 discloses after forming the source/drain contacts, performing a second etching process to pattern the first 2-D material channel layer (see in particular Figs. 3A-D the 2-D material channel layer element 110 is patterned after the source/drain contacts elements 120 are formed and prior to forming the gate structure element 150, see [0020] “active layer 110 may be a 2D semiconductor active layer formed from a transition metal dichalcogenide (TMD) … source electrode 120”).
The order of patterning the 2-D material channel layer as taught by H1 is incorporated as the order of patterning the 2-D material channel layer of L1, Y1 (see L1 the step between Figs. 7B-8B is changed to be after Fig. 11B).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known order of patterning the 2-D channel layer for another in a similar device to obtain predictable results (see H1 Figs. 3A-D).
24. Regarding Claim 30, L1, H1 disclose the method of claim 29.
L1, H1 do not disclose wherein the semiconductor structure further comprises a second 2-D material charge storage layer between the first 2-D material charge storage layer and the first 2-D material channel layer, wherein performing the first etching process is further to pattern the second 2-D material charge storage layer.
L2 discloses the channel is a stack; the charge storage is a stack (see Fig. 1 and [0015] “the first 2D material sub-layer 104-1 of the first conductive layer 104 may comprise MoS2, MoSe2, WS2, WSe2, combinations thereof, or the like. The second 2D material sub-layer 104-2 of the first conductive layer 104 may also comprise MoS2, MoSe2, WS2, WSe2, combinations thereof, or the like.” Selected as a combination of material for each of the two layers).
The stack for the channel and charge storage respectively as taught by L2 is incorporated as a stack for the channel and charge storage respectively of L1, the combination discloses wherein the semiconductor structure further comprises a second 2-D material charge storage layer between the first 2-D material charge storage layer and the first 2-D material channel layer (the 2-D material storage layer of L1 is combined to be a stack of different material layers having a second 2-D material charge storage layer between the first 2-D material charge storage layer and the first 2-D material channel layer), wherein performing the first etching process is further to pattern the second 2-D material charge storage layer (see L1 Fig. 9B the second 2-D material charge storage layer which is still part of the material charge storage layer would be etched to expose the channel stack).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L2 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known number of layers in 2-D material channel and charge storage layers for another for which the two options are provided as selectable alternatives in a similar device to obtain predictable results (see L1 [0015]).
25. Regarding Claim 31, L1, H1, H2 disclose the method of claim 30, wherein the first 2-D material charge storage layer and the second 2-D material charge storage layer comprise different materials (see L2 [0015] “the first 2D material sub-layer 104-1 of the first conductive layer 104 may comprise MoS2, MoSe2, WS2, WSe2, combinations thereof, or the like. The second 2D material sub-layer 104-2 of the first conductive layer 104 may also comprise MoS2, MoSe2, WS2, WSe2, combinations thereof, or the like.” Selected as a combination such that they’re different material).
26. Regarding Claim 34, L1, H1 disclose the method of claim 29, wherein after depositing the gate dielectric layer, the gate dielectric layer is in contact with sidewalls of the patterned first 2-D material channel layer (see L1 Fig. 1B the gate dielectric layer is in contact with an entire height of the 2-D material channel and charge storage layer structures which is inclusive of the patterned first 2-D material channel layer).
27. Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0266059 A1), hereinafter as L1, in view of in view of Huang et al. (US 2021/0018780 A1), hereinafter as H1, in view of Yeom et al. (US 2019/0044009 A1), hereinafter as Y2
28. Regarding Claim 32, L1, H1 disclose the method of claim 29.
L1, H1 do not disclose wherein the first etching process is an atomic layer etching process.
Y2 discloses wherein the first etching process is an atomic layer etching process (see [0084] “ALE process may be etching using plasma” and [0013] 2-D material can include molybdenum or tungsten with chalcogen of selenium or sulfur).
The atomic layer etching process as taught by Y2 is incorporated as an atomic etching process of L1,Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y2 with L1,H1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known method of etching 2-D material for another to obtain predictable results (see Y2 [0084]).
29. Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0266059 A1), hereinafter as L1, in view of in view of Huang et al. (US 2021/0018780 A1), hereinafter as H1, in view of Lin et al. (US 2016/0379901 A1), hereinafter as L2
30. Regarding Claim 33, L1, H1 disclose the method of claim 29.
L1, H1 do not disclose wherein the semiconductor structure further comprises a second 2-D material channel layer between the first 2-D material channel layer and the substrate, wherein performing the second etching process is further to pattern the second 2-D material channel layer.
L2 discloses the channel is a stack; the charge storage is a stack (see Fig. 1 and [0015] “the first 2D material sub-layer 104-1 of the first conductive layer 104 may comprise MoS2, MoSe2, WS2, WSe2, combinations thereof, or the like. The second 2D material sub-layer 104-2 of the first conductive layer 104 may also comprise MoS2, MoSe2, WS2, WSe2, combinations thereof, or the like.” Selected as a combination of material for each of the two layers).
The stack for the channel and charge storage respectively as taught by L2 is incorporated as a stack for the channel and charge storage respectively of L1, the combination discloses wherein the semiconductor structure further comprises a second 2-D material channel layer between the first 2-D material channel layer and the substrate (the 2-D material channel layer of L1 is combined to be a stack of different material layers having a second 2-D material channel layer between the first 2-D material charge channel layer and the substrate), wherein performing the second etching process is further to pattern the second 2-D material channel layer (see L1 Figs. 7B-8B both the entire 2-D material channel and the 2-D material charge storage have the second etching process to decrease the lateral width which is inclusive of the combined second 2-D material channel layer).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L2 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known number of layers in 2-D material channel and charge storage layers for another for which the two options are provided as selectable alternatives in a similar device to obtain predictable results (see L1 [0015]).
Conclusion
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/SAMUEL PARK/Examiner, Art Unit 2818