DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Invention I (Claims 1-7) in the reply filed on December 23rd, 2025 is acknowledged.
Claim 8 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected invention II, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MITANI et al. (Pub. No.: US 2020/0168732 A1), hereinafter as MITANI.
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Regarding claim 1, MITANI discloses a semiconductor device in Figs. 1-3 comprising: a semiconductor layer (combination of layers 11, 12, 13, 14, 15, 17, 18, 19 and 20) divided into a cell section (portion of cell region 1), an outer peripheral section (portion of the outer peripheral region 2), and a boundary section (a region including the boundary between regions 1 and 2), the outer peripheral section having a closed loop shape surrounding the cell section (the outer peripheral region 2 must have closed loop to surround cell region 1) (see annotated Fig. 3 above), the boundary section disposed between the cell section and the boundary section and having a closed loop shape surrounding the cell section (the annotated boundary section also have similar shape with the outer peripheral region 2) (see [0046]); and a trench gate (gate electrode 23/gate insulating film 22) disposed on a main surface of the semiconductor layer (upper surface of layers 19 and 20) (see Fig. 1 and [0060]), wherein the semiconductor layer includes a drift region of a first conductivity type (n-type drift layer 16) disposed in the cell section, the boundary section, and the outer peripheral section (see Figs. 1-3 and [0055]), a body region of a second conductivity type (p-type base region 18) disposed on the drift region at least in the cell section and the boundary section (see Figs. 1-3 and [0057]), a source region of the first conductivity type (n type source region 19) disposed on the body region in the cell section (see Fig. 1 and [0057]), a plurality of bottom regions of the second conductivity type (plurality of first deep layers 14) disposed in the cell section and the boundary section, located at a plurality of positions deeper than the trench gate, and repeatedly arranged at an interval (spacing between 2 first deep layers 14) at least in one direction (y direction) so that the drift region is disposed between the plurality of bottom regions (layer 13 of drift layer 16 in between plurality of first deep layers 14) (see Fig. 1, annotated Fig. 3 above and [0050-0053]), and a plurality of connecting regions of the second conductivity type (plurality of second deep layers 17) disposed in the cell section and the boundary section, located between the plurality of bottom regions and the body region in a thickness direction of the semiconductor layer, being in contact with the plurality of bottom regions and the body region, and repeatedly arranged at an interval (spacing between 2 second deep layers 17) at least in one direction (x direction) so that the drift region is disposed between the plurality of connecting regions (layer 15 of drift layer 16 in between plurality of second deep layers 17) (see Fig. 2, annotated Fig. 3 above and [0056-0057]), and wherein the trench gate is disposed in the cell section, and extends from the main surface of the semiconductor layer into the drift region disposed between the plurality of connecting regions through the source region and the body region (trench gate including gate electrode 23/gate insulating film 22 disposed between second deep layers 17 through source region 19 and base region 18) (see Figs. 1-2).
Regarding claim 7, MITANI discloses the semiconductor device according to claim 1, wherein the semiconductor layer is made of silicon carbide (see [0047], [0049], [0063], [0068] and [0070]).
Allowable Subject Matter
Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Wherein the plurality of bottom regions includes a plurality of cell-section bottom regions disposed in the cell section and a plurality of boundary-section bottom regions disposed in the boundary section, the plurality of cell-section bottom regions is repeatedly arranged at an interval in a first direction in plan view of the semiconductor layer, the plurality of boundary-section bottom regions has a closed loop shape surrounding the cell section and is repeatedly arranged at an interval in a radial direction, a plurality of connecting regions includes a plurality of cell-section connecting regions disposed in the cell section, and in plan view of the semiconductor layer, the plurality of cell-section connecting regions is repeatedly arranged at an interval in a second direction different from the first direction as recited in claim 2. Claims 3-5 depend on claim 2, and therefore also include said claimed limitation.
wherein the plurality of connecting regions includes a plurality of boundary-section connecting regions disposed in the boundary section and a plurality of cell-section connecting regions disposed in the cell section, and a width of the plurality of boundary-section connecting regions in a lateral direction is 10 times or less of a width of the plurality of cell-section connecting regions in a lateral direction as recited in claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818