DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-17, in the reply filed on May 29, 2026 is acknowledged.
Accordingly, claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 29, 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10, 13, and 14 is/are rejected under 35 U.S.C. 102(a)(2) as being antcipated by Sharma et al (US Pub 2023/0209800).
In re claim 10, Sharma et al discloses an integrated circuit (IC) device comprising: a device region (i.e. 652) comprising a plurality of transistors (i.e. see at least paragraph 0029 disclosing devices such as transistors are patterned in the substrate); a dummy interconnect region (i.e. 664) comprising a plurality of metal layers, the dummy interconnect region over the device region and not coupled to the plurality of transistors; and a microfluidic cooling layer (i.e. 670) over the dummy interconnect region, the microfluidic cooling layer comprising a plurality of microfluidic channels (i.e. see at least Figure 6D; paragraph 0050).
In re claim 13, Sharma et al discloses the microfluidic cooling layer comprising a carrier wafer having the plurality of microfluidic channels formed therein (i.e. see at least paragraph 0049).
In re claim 14, Sharma et al discloses further comprising a bonding interface between the dummy interconnect region and the microfluidic cooling layer (i.e. see at least Figure 6D).
Allowable Subject Matter
Claims 1-9 are allowed.
The following is an examiner’s statement of reasons for allowance: The closest prior art of Sharma et al (US Pub 2023/0209800) either singularly or in combination fails to anticipate or render obvious an integrated circuit (IC) device comprising: a first interconnect region comprising a first plurality of metal layers; a device region comprising a plurality of transistors, the device region over the first interconnect region; a second interconnect region comprising a second plurality of metal layers, the second interconnect region over the device region; and a microfluidic channel over the second interconnect region as recited in claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 11, 12, and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Rahman et al (US Pub 2024/0188212)
b. Marin et al (US Pub 2024/0162158)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY HO/Primary Examiner, Art Unit 2817
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