DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 03/14/2023 has been considered.
Drawings
The drawings filed on 03/14/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 03/14/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 9, 10, 15, 16, 17, 19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Nakagawa (2015/0079762).
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Regarding claims 1 and 11, Nakagawa (2015/0079762) discloses:
A semiconductor package, comprising:
a redistribution wiring layer (32 and 33 taken together, ¶0063, ¶0064) having a first surface and a second surface opposite to the first surface (¶0062);
a conductive bump (3BP, ¶0067) on the first surface; and
a first semiconductor device (31, ¶0061) on the conductive bump (at least through wiring layers 33, 32), wherein the redistribution wiring layer includes:
a plurality of redistribution wirings having an uppermost redistribution wiring (32, ¶0063), the uppermost redistribution wiring having a redistribution via and a redistribution line (32) on the redistribution via (¶0063);
a bonding pad (3PD, ¶0067) on the redistribution line (32, ¶0063 lines 10-13);
an uppermost insulating layer (34, ¶0066) on the uppermost redistribution wiring, wherein the uppermost insulating layer (34) overlaps the redistribution line (32) and a first portion of the bonding pad (3PD); and
an opening in the uppermost insulating layer, wherein the opening exposes a second portion of the bonding pad from the uppermost insulating layer, and wherein the conductive bump (3BP) is on the second portion of the bonding pad (3PD).
Regarding claim 5, Nakagawa further discloses:
wherein the bonding pad (3PD) has a first thickness from an upper surface of the redistribution line (32), and wherein the uppermost insulating layer (34) has a second thickness greater than the first thickness from the upper surface of the redistribution line (32, figure 6).
Regarding claim 9, Nakagawa further discloses:
wherein the bonding pad further includes a plating pattern that contacts the conductive bump, and wherein the plating pattern includes gold (¶0140).
Regarding claim 10, Nakagawa further discloses:
wherein the opening has a first diameter at an upper surface of the uppermost insulating layer (34) and a second diameter smaller than the first diameter at a lower surface of the uppermost insulating layer opposite to the upper surface of the uppermost insulating layer (figure 6).
Regarding claim 15, Nakagawa further discloses:
wherein the first portion of the bonding pad ((3PD) includes a portion of a side surface of the bonding pad (figure 6).
Regarding claim 16, Nakagawa further discloses:
wherein the opening in the uppermost insulating layer has a tapered shape (figure 6).
Regarding claim 17, Nakagawa further discloses:
wherein the bonding pad (3PD) has a first thickness from an upper surface of the redistribution line (32), and the uppermost insulating layer (34) has a second thickness greater than the first thickness from the upper surface of the redistribution line (figure 6).
Regarding claim 19, Nakagawa further discloses:
wherein the forming the opening further includes forming the opening to have a first diameter at an upper surface of the uppermost insulating layer and a second diameter smaller than the first diameter at a lower surface of the uppermost insulating layer opposite to the upper surface of the uppermost insulating layer (figure 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa.
Regarding claim 6, Nakagawa does not disclose “6. The semiconductor package of claim 5, wherein the second thickness of the uppermost insulating layer is within a range of 5 micrometers to 30 micrometers”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Regarding claim 18, Nakagawa does not disclose “18. The method of claim 17, wherein the second thickness of the uppermost insulating layer is within a range of 5 micrometers to 30 micrometers”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Allowable Subject Matter
Regarding claim 2, the prior art does not disclose “a molding member on the redistribution wiring layer, wherein the molding member is on the first semiconductor device; a conductive structure that penetrates a portion of the molding member that does not overlap the first semiconductor device in a direction perpendicular to the first semiconductor device and is electrically connected to the bonding pad; and an upper redistribution wiring layer on the molding member and electrically connected to the redistribution wiring layer through the conductive structure” in combination with the remaining claimed features.
Regarding claim 4, the prior art does not disclose “wherein the second portion of the bonding pad that is exposed by the opening includes an upper surface of the bonding pad and a portion of a side surface of the bonding pad” in combination with the remaining claimed features.
Regarding claim 7, the prior art does not disclose “the bonding pad further includes a seed layer pattern that contacts the redistribution line, and wherein the seed layer pattern includes titanium, titanium nitrogen compound, titanium oxygen compound, chromium nitrogen compound, titanium carbon nitrogen compound and/or titanium aluminum nitrogen compound” in combination with the remaining claimed features.
Regarding claim 12, the prior art does not disclose “forming a conductive bump on the second portion of the bonding pad; mounting a first semiconductor device on the conductive bump; forming a molding member on the plurality of insulating layers, wherein the molding member is on the first semiconductor device; forming a conductive structure that penetrates the molding member, wherein the conductive structure does not overlap the first semiconductor device in a direction perpendicular to the first semiconductor device and is electrically connected to the plurality of redistribution wirings; and forming an upper redistribution wiring layer on the molding member, wherein the upper redistribution wiring layer is electrically connected to the plurality of redistribution wirings through the conductive structure” in combination with the remaining claimed features.
Regarding claim 14, the prior art does not disclose “wherein the second portion of the bonding pad includes an upper surface of the bonding pad and a portion of a side surface of the bonding pad” in combination with the remaining claimed features..
Claim 20 is allowed.
Regarding claim 20, the prior art does not disclose “a molding member on the first redistribution wiring layer, wherein the molding member is on the first semiconductor device; a conductive structure that penetrates the molding member and does not overlap the first semiconductor device in a direction perpendicular to the first semiconductor device; a second redistribution wiring layer on the molding member and electrically connected to the first redistribution wiring layer through the conductive structure; and a second semiconductor device on the second redistribution wiring layer” in combination with the remaining claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899