Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species V in the reply filed on 7/31/25 is acknowledged. The traversal is on the ground(s) that the species share a common structure and property as the main technical feature of the application. This is not found persuasive because elections does not fall under Lack of Unity as the instant application is not related to a 371 application. Each species has a variant on the interconnect structure depicted as well as its connections to other devices on the substrate and the structure of those devices. Searching the nonobvious variants of the six different species would be a burden on the examiner.
The requirement is still deemed proper and is therefore made FINAL.
Claims 10-12 and 16-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. It is believed that the source/drain/gate electrode being the same as the second conductive layer only applies to fig. 7 wherein M3 serves as the second conductive layer as well as a gate electrode and a source electrode to the transistors in the figure, respectively. Figure 5 does not contain the light shielding layer of claims 16-17. Applicant timely traversed the restriction (election) requirement in the reply filed on 7/31/25
Claim Rejections - 35 USC § 112
Claims 1, 4 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4 and 6 recites the limitation "the first via” . There is insufficient antecedent basis for this limitation in the claim. Claim 1 does not mention a first via.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao et al. (US Patent 10,283,443).
Claim 1: Liao teaches (Fig. 1) an electronic device, comprising: a substrate (101); a first conductive layer (109), disposed on the substrate; a first insulating layer (108), disposed on the first conductive layer; a second conductive layer (115), disposed on the first insulating layer, wherein the second conductive layer is electrically connected to the first conductive layer; a second insulating layer (116), disposed on the second conductive layer and having a second via; a bonding structure (118), disposed on the second insulating layer, wherein the bonding structure is electrically connected to the second conductive layer through the second via; and a chip, disposed on the bonding structure (Col. 9-10).
Claim 2: Liao teaches (Fig. 1) the first conductive layer is a multi-layer structure. There are multiple parts to (110)
Claim 3: Liao teaches (Col. 2 lines 43-59) the first conductive layer comprises a copper layer.
Claim 4: Liao teaches (Fig. 1) a third conductive layer (110), disposed between the first insulating layer and the second conductive layer; and a third insulating layer (113), disposed between the third conductive layer and the second conductive layer, and having a third via, wherein the first insulating layer has a first via, the second conductive layer is electrically connected to the third conductive layer through the third via, and the third conductive layer is electrically connected to the first conductive layer through the first via.
Claim 6: Liao teaches (Fig. 1) a third conductive layer (110), disposed between the first insulating layer and the second conductive layer; a third insulating layer (113), disposed between the third conductive layer and the second conductive layer, and having a third via, a fourth conductive layer (112), disposed between the third insulating layer and the second conductive layer; and a fourth insulating layer (114), disposed between the fourth conductive layer and the second conductive layer, and having a fourth via, wherein the first insulating layer has a first via, the second conductive layer is electrically connected to the fourth conductive layer through the fourth via, the fourth conductive layer is electrically connected to the third conductive layer through the first via, and the third conductive layer is electrically connected to the first conductive layer through the first via.
Claim 8: Liao teaches (Fig. 1) the first conductive layer (109a) does not overlap with the chip and/or the bonding structure (118) in a top view direction of the substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 7, 9, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US Patent 10,283,443), as applied to claim 4 above, and further in view of Sharma et al (US PGPub 2023/0067765).
Regarding claim 5, as described above, Liao substantially reads on the invention as claimed, except Liao does not teach a semiconductor layer disposed between the second conductive layer and the third conductive layer. Sharma teaches (Fig. 16A) a semiconductor layer disposed between the second conductive layer and the third conductive layer providing increased density within the chip [0028]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Liao to have had the semiconductor layer disposed between the second conductive layer and the third conductive layer to provide memory cells within the interconnects providing increased density within the chip [0028] as taught by Sharma.
Claim 7: Sharma teaches a semiconductor layer, disposed between the first insulating layer and the fourth conductive layer.
Claim 9: Sharma teaches [0059] a driving element, disposed on the substrate and comprising a gate, a source, a drain, and a semiconductor layer, wherein the driving element is electrically connected to the chip; and a storage capacitor, disposed on the substrate and electrically connected to the drain of the driving element, wherein a material of the semiconductor layer comprises metal oxide or low temperature polysilicon.
Claim 13: Sharma teaches (Fig. 16A) the driving element partially overlaps the first conductive layer in a top view direction of the substrate.
Claim 18: Sharma teaches (Fig. 16A) [0059] a wiring (618), disposed on the second insulating layer (504 above M8), wherein the wiring is electrically connected to the source of the driving element (120) and the first conductive layer (M5).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US Patent 10,283,443) and Sharma et al (US PGPub 2023/0067765), as applied to claim 9 above, and further in view of Han et al (US PGPub 2016/0132148).
Regarding claim 14, as described above, Liao and Sharma substantially read on the invention as claimed, except Liao and Sharma do not teach the storage capacitor comprises a first storage electrode and a second storage electrode, wherein the first storage electrode and the gate of the driving element belong to a same layer, and the second storage electrode belongs to a same layer as the source and the drain of the driving element. Han teaches teach the storage capacitor (Cst) comprises a first storage electrode and a second storage electrode, wherein the first storage electrode and the gate of the driving element (Qd) belong to a same layer, and the second storage electrode belongs to a same layer as the source and the drain of the driving element as common in the art (See other references in PTO-892). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Liao and Sharma to have had the layout claimed as it is common in the art.
Claim 15: Han teaches (Fig. 8) [0109] the first storage electrode is electrically connected to a scan line, and the second storage electrode is electrically connected to a data line.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US Patent 10,283,443), as applied to claim 1 above, and further in view of Choi et al. (US PGPub 2021/0365156).
Regarding claim 19, as described above, Liao substantially reads on the invention as claimed, except Liao does not teach the chip is a capacitive modulating element. Choi teaches teach the chip is a capacitive modulating element to incorporate a touch screen application [0013-0016]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Liao to have had a capacitive modulating element to incorporate a touch screen application [0013-0016] as taught by Choi.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US Patent 10,283,443), as applied to claim 1 above, and further in view of Kim et al. (US PGPub 2017/0352834).
Regarding claim 20, as described above, Liao substantially reads on the invention as claimed, except Liao does not teach a drive element, wherein the drive element is a circuit chip. Kim teaches a drive element, wherein the drive element is a circuit chip to drive apply voltage to the display unit [0036]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Liao to have had the drive element is a circuit chip to drive apply voltage to the display unit [0036] as taught by Kim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814