Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The applicant's arguments are moot in light of the new rejection which still uses the same art, the core layer has been redefined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 12 is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable over Lin et al. (US 9854671 B1)
Regarding Claim 1 – Lin teaches a package carrier board integrated with a magnetic element structure (Fig 4C, 120), comprising: a core layer (Fig 10A, 140 + 110 + 150), which has an opposite first surface and a second surface, and each of the first surface and the second surface has a patterned conductive circuit layer (Fig 10, the unlabeled circuits connected to the solder bumps 190, and described in col 8, lines 45 -50 which states that a circuit is placed between the layer 140 and layer 170); a magnetic element structure, comprising: a plurality of patterned magnetic conductive metal layers, which are stacked at intervals and embedded in the core layer, and each has at least one magnetic conductive metal, wherein part of the magnetic conductive metals constitutes an array block (Fig 4C, 120-124); a plurality of patterned conductive coil layers, which are embedded in the core layer, wherein part of the patterned conductive coil layer is framed to surround the array block (Fig 8A, 162, 164, and 166); and a conductive connecting element, which is disposed through the core layer and electrically connects the first surface of the core layer and the patterned conductive circuit layer of the second surface (Fig 10A, 164 on the right showing connection between top and bottom surfaces).
Regarding Claim 2 – Lin teaches the package carrier board integrated with a magnetic element structure of claim 1, wherein each patterned magnetic conductive metal layer has a plurality of magnetic conductive metal elements in block shape (Fig 10A; Definition of ‘block’ from Oxford Languages Dictionary – “a large solid piece of hard material, especially rock, stone, or wood, typically with flat surfaces on each side”), strip shape, or fin shape and fig 4c shows the conductive metal elements has a rectangular shape which would qualify as a block)
Regarding Claim 3 – Lin teaches the package carrier board integrated with a magnetic element structure of claim 1, wherein the patterned magnetic conductive metal layer is made of iron (Fe), nickel (Ni), cobalt (Co), zinc (Zn), an alloy containing at least two of them or more, or in an alloy doped with manganese (Mn), molybdenum (Mo), boron (B), copper (Cu) or vanadium (V) (Col 4, lines 33-39).
Regarding Claim 12 – Lin teaches the package carrier board integrated with a magnetic element structure of claim 1, further comprising: a first circuit build-up layer structure, which is disposed on the first surface of the core layer (Lin; Fig 10A, 140 & 162) and has a plurality of first insulating layers (Fig 10A, 140 & 170) and a plurality of first conductive circuit layers (Fig 10A, 162 and additional layers between 140 & 170), wherein the first conductive circuit layers are stacked and covered in the first insulating layer (Fig 10A, showing stacked configuration between 140 & 170); and a second circuit build-up layer structure, which is disposed on the second surface of the core layer (Fig 10A, 150 &166) and has a plurality of second insulating layers and a plurality of second conductive circuit layers, wherein the second conductive circuit layers are stacked and covered in the second insulating layer (Fig 10A, layers between 150 & 180).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9854671 B1) in view of Kondo et al. (US 20240177911 A1)
Regarding Claim 4 – Lin teaches the package carrier board integrated with a magnetic element structure of claim 1, but fails to disclose wherein the core layer is a plurality of insulating layers that are stacked, and its material includes organic photosensitive dielectric materials, organic non-photosensitive dielectric materials and/or inorganic oxide materials.
Kondo wherein the core layer is a plurality of insulating layers that are stacked (Fig 2, 40), and its material includes organic photosensitive dielectric materials, organic non-photosensitive dielectric materials and/or inorganic oxide materials (Kondo [0021] states “stacking a plurality of insulating layers 40. The insulating material for the insulating layers 40 is not particularly limited, but includes, for example, borosilicate glass and an inorganic filler. Examples of the inorganic filler include a glass powder and a ceramic aggregate such as alumina”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Lin with the core layer is a plurality of insulating layers that are stacked, and its material includes organic photosensitive dielectric materials, organic non-photosensitive dielectric materials and/or inorganic oxide materials as taught by Kondo because Kondo [0008] states “can reduce the shrinkage percentage of the inner electrode during firing, can improve the resolution at the time of photolithographic patterning, and can reduce the electrical resistance of the inner electrode after firing”.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9854671 B1) in view of Dai et al. (US 20220191361 A1)
Regarding Claim 5 – Lin teaches the package carrier board integrated with a magnetic element structure of claim 1, but fails to disclose wherein the patterned conductive coil layers are helical coil-shaped inductive wiring, solenoid coil-shaped inductive wiring, or toroidal coil-shaped inductive wiring.
Dai teaches the patterned conductive coil layers are helical coil-shaped inductive wiring, solenoid coil-shaped inductive wiring, or toroidal coil-shaped inductive wiring (Fig 2, Dai [0034] states “Each of the coils 3213 has a helical structure, in shape of a square, a race track, or a circle”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Lin with the patterned conductive coil layers are helical coil-shaped inductive wiring, solenoid coil-shaped inductive wiring, or toroidal coil-shaped inductive wiring as taught by Dai because Dai [0034] states “A ratio of the thickness H1 to the wire pitch S is greater than 3, so that a resistance of each coil 3213 is reduced on the basis of ensuring the effective length of each coil 3213, reducing a power consumption of the camera module 100.”
Regarding Claim 6 – Lin in view of Dai teaches the package carrier board integrated with a magnetic element structure of claim 1, wherein the patterned conductive coil layer is made of copper, copper alloy, nickel, or silver (Fig 2, Dai [0034]).
Claim(s) 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9854671 B1) in view of Lee et al. (US 20180061550 A1)
Regarding Claim 7 – Lin teaches the package carrier board integrated with a magnetic element structure of claim 1, but fails to disclose further comprising: a plurality of rigid support layers, which is embedded in the core layer and adjacent to the patterned conductive coil layers.
Lee teaches a plurality of rigid support layers (Fig 2, 20), which is embedded in the core layer (Fig 2, 55) and adjacent to the patterned conductive coil layers (Fig 2, 41 & 42).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Lin with a plurality of rigid support layers, which is embedded in the core layer and adjacent to the patterned conductive coil layers as taught by Lee to support the coil patterns and maintain rigidity (Lee [0078]).
Regarding Claim 8 – Lin in view of Lee teaches the package carrier board integrated with a magnetic element structure of claim 7, wherein each rigid support layer has a plurality of support members in block shape, strip shape, or fin shape (Lee; Fig 2, Definition of ‘block’ from Oxford Languages Dictionary – “a large solid piece of hard material, especially rock, stone, or wood, typically with flat surfaces on each side”), strip shape, or fin shape.
Regarding Claim 9 – Lin in view of Lee teaches the package carrier board integrated with a magnetic element structure of claim 7, wherein the material of the rigid support layer is copper (Cu), stainless steel, ceramics, plastic steel, iron (Fe), nickel (Ni), cobalt (Co), zinc (Zn), containing two or more alloys, or alloys doped with manganese (Mn), molybdenum (Mo), boron (B), copper (Cu), or vanadium (V) (Lee [0078]).
Regarding Claim 10 – Lin in view of Lee teaches the package carrier board integrated with a magnetic element structure of claim 7, further comprising: a first circuit build-up layer structure, which is disposed on the first surface of the core layer (Lin; Fig 10A, 140 & 162) and has a plurality of first insulating layers (Fig 10A, 140 & 170) and a plurality of first conductive circuit layers (Fig 10A, 162 and additional layers between 140 & 170), wherein the first conductive circuit layers are stacked and covered in the first insulating layer (Fig 10A, showing stacked configuration between 140 & 170); and a second circuit build-up layer structure, which is disposed on the second surface of the core layer (Fig 10A, 150 &166) and has a plurality of second insulating layers and a plurality of second conductive circuit layers, wherein the second conductive circuit layers are stacked and covered in the second insulating layer (Fig 10A, layers between 150 & 180).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9854671 B1) in view of Lee et al. (US 20180061550 A1) and in further view of Cho et al. (US 20220159839 A1)
Regarding Claim 11 – Lin in view of Lee teaches the package carrier board integrated with a magnetic element structure of claim 10, but fails to disclose wherein another magnetic element structure is embedded in the first circuit build-up layer structure and/or the second circuit build-up layer structure.
Cho teaches another magnetic element structure is embedded in the first circuit build-up layer structure and/or the second circuit build-up layer structure (Fig 3, 200; Cho [0008] & [0038]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Lin with another magnetic element structure is embedded in the first circuit build-up layer structure and/or the second circuit build-up layer structure as taught by Cho because Cho [0051] states “the plurality of magnetic members 200, inductance performance may be improved.”.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9854671 B1) in view of Cho et al. (US 20220159839 A1)
Regarding Claim 13 – Lin teaches the package carrier board integrated with a magnetic element structure of claim 12, but fails to disclose wherein another magnetic element structure is embedded in the first circuit build-up layer structure and/or the second circuit build-up layer structure.
Cho teaches another magnetic element structure is embedded in the first circuit build-up layer structure and/or the second circuit build-up layer structure (Fig 3, 200; Cho [0008] & [0038]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Lin with another magnetic element structure is embedded in the first circuit build-up layer structure and/or the second circuit build-up layer structure because Cho [0051] states “the plurality of magnetic members 200, inductance performance may be improved.”.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9854671 B1) in view of Jeon et al. (US 20130337268 A1)
Regarding Claim 7 – Lin teaches the package carrier board integrated with a magnetic element structure of claim 1, but fails to disclose further comprising: a plurality of rigid support layers, which is embedded in the core layer and adjacent to the patterned conductive coil layers.
Jeon teaches a plurality of rigid support layers, which is embedded in the core layer and adjacent to the patterned conductive coil layers (Fig 1, Jeon [0037-0038]; 110 & 131).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the core layer and the conductive patterned coil layers of Lin with a plurality of rigid support layers, which is embedded in the core layer and adjacent to the patterned conductive coil layers as taught by Jeon to maintain rigidity (Jeon [0037] and [0038]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADITYA SHARMA whose telephone number is (571)270-7246. The examiner can normally be reached Monday - Friday 8:30 - 5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847