DETAILED ACTION
This action is responsive to the amendment filed October 7, 2025. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-7, and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US 2023/0284450, newly cited)
(Re Claim 1) Lee teaches an integrated circuit (IC) structure, comprising (see Figs. 5B-6B):
a plurality of semiconductor devices (PTR) on a substrate, substrate (10);
an inter-layer dielectric (ILD 51) structure over the semiconductor devices;
an interconnect (PLP, PCP) in the ILD structure and electrically connected to the semiconductor devices;
a first dielectric layer (53 or 55, ¶62) over the ILD structure;
an etching barrier layer (SE) on the first dielectric layer;
a conductive layer (SC or SC+SP, ¶67) on the etching barrier layer;
a plurality of memory units stacked in a vertical direction over the etching barrier layer (memory array in ST1, ST2); and
a dielectric material (DSP or just BLK) disposed within a vertical channel opening of the plurality of memory units, the dielectric material being in contact with the etching barrier layer (Figs. 5B, 6A), the dielectric material having a stepped sidewall structure comprising an upper portion with an upper sidewall and a lower portion with a lower sidewall horizontally offset from the upper sidewall, and a horizontal surface connecting the lower sidewall to the upper sidewall, the upper portion tapering inward toward the horizontal surface and the lower portion flaring outward toward the horizontal surface (see Fig. 6B).
(Re Claim 2) wherein the etching barrier layer is made of a different material than the first dielectric layer (¶¶62, 66, 102).
(Re Claim 4) wherein the etching barrier layer comprises tungsten, titanium, titanium nitride, or combinations thereof (¶102).
(Re Claim 5) wherein the etching barrier layer is made of metal oxide (¶66, 102).
(Re Claim 6) wherein the etching barrier layer is made of a same material as the conductive layer and has a thicker thickness than the conductive layer (see Figs. 5B, 6A, ¶¶66-67, e.g. doped polysilicon).
(Re Claim 7) further comprising: a second dielectric layer (Fig. 6A, CIL, ¶85) sandwiched between the etching barrier layer and the conductive layer.
(Re Claim 10) a source line extending upwardly from the conductive layer and electrically connected to the memory units, wherein the etching barrier layer further laterally extends between the semiconductor devices and the source line (see Figs. 1 and 14, the source line is unlabeled in Fig. 14, second from right, extending upwardly from SP).
Second rejection with alternative mapping
Claims 1-3 and 7-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US 2023/0284450, newly cited).
(Re Claim 1) Lee teaches an integrated circuit (IC) structure, comprising (see Figs. 5B-6B):
a plurality of semiconductor devices (PTR) on a substrate, substrate (10);
an inter-layer dielectric (ILD 51) structure over the semiconductor devices;
an interconnect (PLP, PCP) in the ILD structure and electrically connected to the semiconductor devices;
a first dielectric layer (53 or 55, ¶62) over the ILD structure;
an etching barrier layer (SP) on the first dielectric layer;
a conductive layer (GE1, ¶72) on the etching barrier layer;
a plurality of memory units stacked in a vertical direction over the etching barrier layer (memory array in ST1, ST2); and
a dielectric material (DSP or just BLK) disposed within a vertical channel opening of the plurality of memory units, the dielectric material being in contact with the etching barrier layer (Figs. 5B, 6A), the dielectric material having a stepped sidewall structure comprising an upper portion with an upper sidewall and a lower portion with a lower sidewall horizontally offset from the upper sidewall, and a horizontal surface connecting the lower sidewall to the upper sidewall, the upper portion tapering inward toward the horizontal surface and the lower portion flaring outward toward the horizontal surface (see Fig. 6B).
(Re Claim 2) wherein the etching barrier layer is made of a different material than the first dielectric layer (¶¶106, 62).
(Re Claim 3) wherein the etching barrier layer is made of a carbon-containing material (¶106).
(Re Claim 7) further comprising: a second dielectric layer (ILD1, ¶109) sandwiched between the etching barrier layer and the conductive layer.
(Re Claim 8) wherein the second dielectric layer is made of a same material as the first dielectric layer and different than the etching barrier layer (¶¶62,106,109, first dielectric may be silicon oxide).
(Re Claim 9) wherein the second dielectric layer is made of a different material than the first dielectric layer and the etching barrier layer (¶¶62,106,109, first dielectric may be silicon nitride).
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related memory devices having a plurality of insulating, conductive, and etch stop layers between the peripheral circuit devices and the memory cell array.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898