Prosecution Insights
Last updated: April 19, 2026
Application No. 18/184,413

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

Non-Final OA §102
Filed
Mar 15, 2023
Examiner
CHEN, DAVID Z
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co. Ltd.
OA Round
1 (Non-Final)
44%
Grant Probability
Moderate
1-2
OA Rounds
3y 9m
To Grant
94%
With Interview

Examiner Intelligence

Grants 44% of resolved cases
44%
Career Allow Rate
299 granted / 675 resolved
-23.7% vs TC avg
Strong +49% interview lift
Without
With
+49.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
63 currently pending
Career history
738
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
47.4%
+7.4% vs TC avg
§102
26.4%
-13.6% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 675 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment/Restriction Applicant’s election without traverse of Invention I and Claims 1-5 in the reply filed on December 18, 2025 is acknowledged. However, Claim 3 appears to read on non-elected FIG. 4 as disclosed in [0059] of the Specification. Thus, Claims 3 and 6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention. Election was made without traverse in the reply filed on December 18, 2025. Specification The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-2 and 4-5 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2008/0001278 A1 to Matsumoto (“Matsumoto”). As to claim 1, Matsumoto discloses a semiconductor apparatus, comprising: a semiconductor device (power semiconductor element ¶ 0037); an insulating substrate (1) including a circuit board (wiring pattern ¶ 0037) that is electrically connected to the semiconductor device (power semiconductor element ¶ 0037); and a terminal member (31) having a main terminal (at 34) connectable to an external conductor (¶ 0059) and a connection terminal (adjacent 39) bonded to the circuit board (wiring pattern ¶ 0037), wherein the connection terminal (adjacent 39) has at least one distal end portion (37) bonded to the circuit board (wiring pattern ¶ 0037), a main body portion (32 on 35a) that rises from the at least one distal end portion (37) and extends toward the main terminal (at 34), and a coupling portion (X) that has a conductive property and is coupled to the main body portion (32 on 35a), the main body portion (32 on 35a) has a main body coupling portion (38) to which the coupling portion (X) is coupled, a cross-sectional area of the coupling portion (X) perpendicular to a direction in which a current flows in the coupling portion (X) is larger than a cross-sectional area of the main body coupling portion (38) perpendicular to a direction in which a current flows in the main body coupling portion (38) (See Fig. 1, Fig. 2, Fig. 14, Fig. 15, ¶ 0037, ¶ 0041, ¶ 0042, ¶ 0059, ¶ 0062, ¶ 0063, ¶ 0065) (Notes: the circuit board is met by the wiring pattern forming circuity connecting elements. Further, the planar cross-sectional area at X is larger than the smaller projection area of the main body coupling portion. Furthermore, the limitation “portion” is defined as a part of any whole, either separated from or integrated with it, the limitation “bond” is defined as to connect or bind, and the limitation “couple” is defined as to bring (two electric circuits or circuit components) close enough to permit an exchange of electromagnetic energy by Dictionary.com, where no direct/physical bonding/coupling is required). PNG media_image1.png 585 908 media_image1.png Greyscale As to claim 2, Matsumoto further discloses wherein the at least one distal end portion (37) includes a plurality of distal end portions (37), and the main body portion (32 on 35a) further includes a plurality of branch sections (vertical 32 on 35a) respectively branching toward respective ones of the plurality of distal end portions (37) (See Fig. 14). As to claim 4, Matsumoto further discloses wherein the coupling portion (X) and the main body portion (32 on 35a) each have a plate shape, a thickness of the coupling portion (X) perpendicular to the direction in which the current flows in the coupling portion (X) is larger than a thickness of the main body portion (32 on 35a) perpendicular to a direction in which a current flows in the main body portion (32 on 35a) (See Fig. 14, Fig. 15) (Notes: the limitation appears to compare a planar thickness t2 to a vertical thickness t1 as shown in FIG. 2 of the Application. Such is met by FIG. 14 and FIG. 15 of Matsumoto). As to claim 5, Matsumoto further discloses wherein the coupling portion (X) is bonded to the circuit board (wiring pattern ¶ 0037) (See Fig. 2, Fig. 14). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID CHEN/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Mar 15, 2023
Application Filed
Jan 06, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12601689
ELECTRONIC PACKAGE HAVING HUMIDITY INDICATOR
2y 5m to grant Granted Apr 14, 2026
Patent 12581634
SEMICONDUCTOR DEVICES INCORPORATING SEMICONDUCTOR LAYER CONFIGURATIONS AND METHODS OF MANUFACTURING THE SAME
2y 5m to grant Granted Mar 17, 2026
Patent 12581755
IMAGING DEVICE COMPRISING NET SHAPE WIRING
2y 5m to grant Granted Mar 17, 2026
Patent 12568849
DAM FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT
2y 5m to grant Granted Mar 03, 2026
Patent 12557691
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE COMPRISING A POLYIMIDE FILM DISPOSED IN AN ACTIVE REGION AND A TERMINATION REGION AND A PASSIVATION FILM DISPOSED AS A FILM UNDERLYING THE POLYIMIDE FILM
2y 5m to grant Granted Feb 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
44%
Grant Probability
94%
With Interview (+49.2%)
3y 9m
Median Time to Grant
Low
PTA Risk
Based on 675 resolved cases by this examiner. Grant probability derived from career allow rate.

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