DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2024/0006342 A1).
Regarding claim 1, Kim et al. discloses an electronic package comprising (See annotated Fig. 5 below):
a package substrate (100) including a front side (FS), a back side (BS), one or more metallization layers (113 redistribution vias; [0024]), and one or more dielectric layers (111, may include dielectric [0021]);
a first die (220) including a face side (DFS) and a back side (DBS) , the back side attached to the front side of the package substrate and facing the one or more metallization layers and the one or more dielectric layers;
a first wire bond (WB, [0048]) connecting the face side of the first die to the front side of the package substrate (through 213, [0049]); and
a molding layer (230) that encapsulates the first die and the wire bond on the package substrate.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Vemuri et al. (US 2023/0059431 A1).
Regarding claim 1, Vemuri et al. discloses an electronic package comprising (See annotated Fig. 1A below):
a package substrate (100) including a front side (FS), a back side (BS), one or more metallization layers (106, interposer includes metallization layers 122, [0027]);
a first die (102(2)) including a face side (DFS) and a back side, the back side attached to the front side of the package substrate and facing the one or more metallization layers (106, interposer includes metallization layers 122, [0027]);
a first wire bond (124, [0027]) connecting the face side of the first die to the front side of the package substrate; and
a molding layer (105) that encapsulates the first die and the wire bond on the package substrate.
Vemuri et al. does not explicitly disclose a dielectric, however one of ordinary skill in the art would understand that a dielectric material would be in between the dielectric layers.
It would have been obvious to one having ordinary in the art before the filing date of the invention that a dielectric material would be included in Vemuri et al., because package substrates having metallization layers are ordinarily formed with dielectric layers between the metallization layers to provide electrical insulation, mechanical support, and routing capability, and the inclusion of such dielectric material would have been a predictable and routine design choice.
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Regarding claim 2, Vemuri et al. discloses an electronic package of claim 1, further comprising a plurality of vertical interconnects (120) extending through a thickness of the molding layer and in contact with the front side of the package substrate.
Vemuri et al. expressly discloses “one or more electrical interconnects” 120, such as conductive pillars, metal pillars, metal posts, or metal vias, disposed between the interposer and the package substrate. (See ¶ [0023], ¶ [0027], and ¶ [0033]).
It would have been obvious to implement these interconnects as a plurality of vertical interconnects extending through the molding layer and contacting the front side of the package substrate in order to provide multiple electrical connection points, increase routing flexibility, and accommodate the electrical interconnection needs of the package assembly.
Regarding claim 3, Vemuri et al. discloses the electronic package of claim 2, wherein the back side of the package substrate is not overmolded.
Once the package of claim 2 is modified to include vertical interconnects extending through the molding layer and contacting the package substrate, it would have been obvious to leave the back side of the package substrate unovermolded because overmolding is typically applied to the active side/package assembly region to encapsulate the dies and wire bonds, while the opposite side of the substrate remains available for board-level mounting and solder interconnection. Such a configuration would have been a predictable packaging choice within the ordinary skill in the art.
Regarding claim 4, Vemuri et al. discloses the electronic package of claim 3, further comprising:
a planarized bottom surface spanning the plurality of vertical interconnects and the molding layer; and
a plurality of solder bumps on the plurality of vertical interconnects.
It would have been obvious to further provide a planarized bottom surface spanning the plurality of vertical interconnects and the molding layer, together with solder bumps on the vertical interconnects, because planarization and solder bump attachment are conventional techniques for preparing a package for downstream assembly and board-level connection. In particular, forming a substantially planar lower surface and mounting solder bumps on the vertical interconnects would have been an obvious and routine implementation to facilitate package attachment and electrical interfacing.
Regarding claim 12, Vemuri et al. discloses the package on package structure comprising:
a first electronic package (104);
a second electronic package mounted on the first electronic package (see annotated Fig. 1A below), the second electronic package comprising:
a package substrate (100) including a front side (FS), a back side (BS), one or more metallization layers (106, interposer includes metallization layers 122, [0027]);
wherein the front side (FS) of the package substrate faces the first electronic package (104);
a first die (102(2)) including a face side (DFS) and a back side, the back side attached to the front side of the package substrate and facing the one or more metallization layers (106, interposer includes metallization layers 122, [0027]);
a first wire bond (124, [0027]) connecting the face side of the first die to the front side of the package substrate; and
a molding layer (105) that encapsulates the first die and the wire bond on the package substrate.
Vemuri et al. does not explicitly disclose a dielectric, however one of ordinary skill in the art would understand that a dielectric material would be in between the dielectric layers.
It would have been obvious to one having ordinary in the art before the filing date of the invention that a dielectric material would be included in Vemuri et al., because package substrates having metallization layers are ordinarily formed with dielectric layers between the metallization layers to provide electrical insulation, mechanical support, and routing capability, and the inclusion of such dielectric material would have been a predictable and routine design choice.
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Regarding claim 13, Vemuri et al. discloses the package on package structure of claim 12, further comprising a plurality of vertical interconnects (120) extending through a thickness of the molding layer and in contact with the front side of the package substrate.
Vemuri et al. expressly discloses “one or more electrical interconnects” 120, such as conductive pillars, metal pillars, metal posts, or metal vias, disposed between the interposer and the package substrate. (See ¶ [0023], ¶ [0027], and ¶ [0033]).
It would have been obvious to implement these interconnects as a plurality of vertical interconnects extending through the molding layer and contacting the front side of the package substrate in order to provide multiple electrical connection points, increase routing flexibility, and accommodate the electrical interconnection needs of the package assembly.
Regarding claim 14, Vemuri et al. discloses the package on package structure of claim 13, wherein the plurality of vertical interconnects (120) is bonded to the first electronic package.
Vemuri et al. does not discloses that the interconnects are bonded via a plurality of package solder bumps; however, it would have been obvious to one of ordinary skill in the art to provide solder bumps at the interface between the plurality of vertical interconnects and the first electronic package because solder bumps are a conventional and predictable means of forming both electrical and mechanical connections in package-on-package assemblies, and their use would have improved assembly compatibility, connection reliability, and manufacturability without changing the basic operation of the disclosed package.
Regarding claim 15, Vemuri et al. discloses the package on package structure of claim 13, wherein the back side of the package substrate is not overmolded.
Once the package of claim 13 is modified to include vertical interconnects extending through the molding layer and contacting the package substrate, it would have been obvious to leave the back side of the package substrate unovermolded because overmolding is typically applied to the active side/package assembly region to encapsulate the dies and wire bonds, while the opposite side of the substrate remains available for board-level mounting and solder interconnection. Such a configuration would have been a predictable packaging choice within the ordinary skill in the art.
Allowable Subject Matter
Claims 5-7, 16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 5–7 and 16–17 are allowable because the prior art of record, including Vemuri et al., does not teach or suggest a second die whose back side faces the face side of the first die together with a second wire bond connecting the face side of the second die directly to the front side of the package substrate. Vemuri et al. routes wire bonds to an interposer rather than directly to the package substrate. Additionally, the cited art does not disclose or suggest the memory-die limitations of claims 6, 7, and 17, including a second memory die having a build-up structure including a low-k dielectric layer. Accordingly, the claimed subject matter as a whole is not rendered obvious by the prior art of record.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630.
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/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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