DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on January 27, 2026. Claims 1 and 9-11 have been amended. No new claims have been added. Claims 14-20 have been canceled. Currently, claims 1-13 are pending.
Applicant’s amendment to claims 1 and 10 successfully overcome the 112(b) rejection of claims 1 and 10 set forth in the previous Office Action.
Response to Arguments
Applicant's arguments filed on January 27, 2026 have been fully considered but they are not persuasive. The amendment specifies that an upper surface of the lower gate electrode is higher than a lowermost end of the integrated insulator. Lin teaches this amendment. Specifically, Lin discloses a gate stack where gate metals 112 and 113 meet at an interface 139 (Para [0054], Figure 1B). This interface 139, representing the upper surface of the lower gate electrode, is situated higher than the bottom surface 137 of the dielectric layer 129 as shown in Figure 1B. Therefore, Lin clearly teaches an embodiment where the upper surface of the lower gate electrode extends above the lowermost end of the integrated insulator.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the claim recites, “an inner layer an outer layer ….” is indefinite as it is not clear whether the two are distinct, separate or single entity as there is no comma or conjunction in between.
Claims 2-8 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-13 is rejected under 35 U.S.C. 103 as being unpatentable over Qin et al. (US 2024/0072146 A1; hereafter Qin) in view of Chan et al. (US 2023/0386928 A1; hereafter Chan) and Lin et al. (US 2023/0307456 A1; hereafter Lin).
Regarding claim 1, Qin teaches an integrated circuit device (see e.g., Figures 1-7) comprising:
an upper transistor (see e.g., stacked transistor structure 100 includes an upper nanosheet transistor, Para [0041], Figures 1B, 5A and 7A) that is on a substrate (see e.g., upper nanosheet transistor disposed on substrate 101, Para [0039], Figures 1B, 5A and 7A) and comprises an upper channel region (see e.g., the upper nanosheet transistor comprises nanosheet channel layers 107, Para [0042], Figures 1B, 5A and 7A) and an upper gate electrode on the upper channel region (see e.g., The upper nanosheet transistors comprise an alternating structure of gate layers 105 and nanosheet channel layers 107, Para [0042], Figure 1B);
a lower transistor (see e.g., stacked transistor structure 100 includes a lower nanosheet transistor, Para [0041], Figures 1B, 5A and 7A) that is between the substrate and the upper transistor (see e.g., the lower nanosheet transistor is between the upper nanosheet transistor and the substrate 101, Figures 1B, 5A and 7A) and comprises a lower channel region (see e.g., the lower nanosheet transistor comprises nanosheet channel layers 107, Para [0042], Figures 1B, 5A and 7A) and a lower gate electrode on the lower channel region (see e.g., The lower nanosheet transistors comprise an alternating structure of gate layers 105 and nanosheet channel layers 107, Para [0042], Figure 1B); and
an integrated insulator that is between the lower channel region and the upper channel region (see e.g., dielectric layer 114 separates the upper nanosheet transistor and the lower nanosheet transistor and is disposed between the lower and upper nanosheet channel layers, Para [0041], Figures 1B, 5A and 7A)
Qin does not explicitly teach
“Integrated insulator….comprises an inner layer an outer layer on the inner layer,
wherein the inner layer and the outer layer comprise different materials”.
In a similar field of endeavor Chan teaches
Integrated insulator….comprises an inner layer an outer layer on the inner layer,
wherein the inner layer and the outer layer comprise different materials (see e.g., middle insulating layer 120 may be formed of an insulating material, such as an oxide or a nitride. For example, the middle insulating layer 120 may comprise or be formed of SiO.sub.2, SiN, SiC, SiCN, SiOCN, SiOBCN or SiON. The middle insulating layer 120 may be formed as a composite layer structure comprising, e.g., a stack of two or more different insulating layers, Para [0080], Figure 1).
Consequently, if the middle insulating layer 120 has a multilayer structure, the outermost material layer would be treated as the outer layer and any material layer situated beneath it would be the inner layer. As these layers are described as being made of different materials, the structure by its very nature comprises an outer and an inner layer of different materials.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chan’s teachings of Integrated insulator….comprises an inner layer an outer layer on the inner layer, wherein the inner layer and the outer layer comprise different materials in the device of Qin as the use of a multilayer dielectric structure is a known technique in semiconductor device manufacturing and is routinely employed to predictably optimize device performance.
Qin does not explicitly teach
“wherein an upper surface of the lower gate electrode is higher than a lowermost end of the integrated insulator”.
In a similar field of endeavor Lin teaches
wherein an upper surface of the lower gate electrode is higher than a lowermost end of the integrated insulator (see e.g., the gate metals 112 and 113 meet at an interface 139. The dielectric layer 129 has a top surface 135 and a bottom surface 137. The interface 139 is lower than a top surface 135 and higher than a bottom surface 137 of the dielectric layer 129. As shown in Figure 1B the interface 139 (that is, upper surface of the lower gate electrode) is higher than the bottom surface 137 of the dielectric layer 129, Para [0054], Figure 1B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of wherein an upper surface of the lower gate electrode is higher than a lowermost end of the integrated insulator in the device of Qin in order to improve device performance and to ensure that there is no work function interference of the upper transistor with the gate metal of the lower transistor.
Regarding claim 2, Qin, as modified by Chan and Lin, teaches the limitations of claim 1 as mentioned above. Qin further teaches
wherein the upper channel region comprises a plurality of upper channel regions, and (see e.g., the upper nanosheet transistor has a plurality of upper nanosheet channel layers 107, Para [0042], Figures 1B, 5A and 7A)
the upper transistor further comprises:
an upper source/drain region contacting the plurality of upper channel regions (see e.g., the upper nanosheet transistor comprises top source/drain region 113 contacting the upper nanosheet channel layers 107, Para [0044], Figures 1B, 5A and 7A);
an upper gate structure on the plurality of upper channel regions; and (see e.g., upper gate layers 105 on the plurality of upper nanosheet channel layers 107, Para [0043], Figures 1B, 5A and 7A)
an upper inner spacer layer that is between the upper source/drain region and the upper gate structure and is between the plurality of upper channel regions (see e.g., upper gate spacers 124/106 between the top source/drain region 113 and the upper gate layers 105 and between the plurality of upper nanosheet channel layers 107, Para [0043], Figures 1B, 5A and 7A),
Qin does not explicitly teach
“wherein the upper inner spacer layer comprises a material different from the outer layer”.
In a similar field of endeavor Lin teaches
wherein the upper inner spacer layer comprises a material different from the outer layer (see e.g., The inner spacers 114 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials without departing from the scope of the present disclosure. In one example, the inner spacers 114 include silicon oxycarbonitride.
The dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials.
The dielectric layer 129 may include multiple layers of different dielectric material between the semiconductor layers 127. For example, a first dielectric layer of silicon oxide may be positioned in contact with each of the semiconductor layers 127. A second dielectric layer of silicon nitride may be positioned between upper and lower portions of the first dielectric layer, Paras [0040], [0052], [0056], Figure 1A).
Lin discloses a structure that includes both the inner spacers and the outer layer that is, the first dielectric layer. Lin discloses a specific example where the first dielectric layer is made of silicon oxide and the inner spacers 114 made of silicon oxycarbonitride, providing a clear example of different materials used for the inner spacers 114 and the first dielectric layer.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of wherein the upper inner spacer layer comprises a material different from the outer layer in the device of Qin as the use of a multilayer dielectric structure is a known technique in semiconductor device manufacturing and is routinely employed to predictably optimize device performance.
Regarding claim 3, Qin, as modified by Chan and Lin, teaches the limitations of claim 2 as mentioned above. Qin further teaches
wherein the upper transistor further comprises a gate spacer on a side surface of an upper portion of the upper gate structure (see e.g., the upper nanosheet transistor comprises a gate spacer 134 on a side surface of an upper portion of the upper gate layers 105, Para [0043], Figure 7A),
the upper inner spacer layer is between the integrated insulator and the gate spacer (see e.g., upper inner spacers 124/106 are between the dielectric layer 114 and the gate spacer 134, Figures 1B, 5A and 7A),
Qin does not explicitly teach
“the gate spacer and the outer layer comprises a same material”.
In a similar field of endeavor Lin teaches
the gate spacer and the outer layer comprises a same material (see e.g., The sidewall spacer 131 may include multiple dielectric layers. Each of the dielectric layers of the sidewall spacer 131 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials.
The dielectric layer 129 may include multiple layers of different dielectric material between the semiconductor layers 127. For example, a first dielectric layer of silicon oxide may be positioned in contact with each of the semiconductor layers 127. A second dielectric layer of silicon nitride may be positioned between upper and lower portions of the first dielectric layer, Paras [0056], [0078], Figure 1A).
Lin teaches the possibility of using the same material for the first dielectric layer and the sidewall spacer. Lin discloses the sidewall spacer 131 can comprise silicon oxide and the first dielectric layer maybe made of silicon oxide.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of the gate spacer and the outer layer comprises a same material in the device of Qin as using the same material for the spacer and outer layer simplifies the manufacturing process.
Regarding claim 4, Qin, as modified by Chan and Lin, teaches the limitations of claim 3 as mentioned above. Qin further teaches
wherein the gate spacer contacts the upper gate structure (see e.g., gate spacer 134 contacts the gate layer 105, Para [0042], Figures 1B, 5A and 7A).
Regarding claim 5, Qin, as modified by Chan and Lin, teaches the limitations of claim 3 as mentioned above. Qin does not explicitly teach
“wherein the gate spacer and the outer layer comprise SiBCN or SiOCN”.
In a similar field of endeavor Lin teaches
wherein the gate spacer and the outer layer comprise SiBCN or SiOCN (see e.g., The sidewall spacer 131 may include multiple dielectric layers. Each of the dielectric layers of the sidewall spacer 131 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials.
The dielectric layer 129 may include multiple layers of different dielectric material between the semiconductor layers 127. For example, a first dielectric layer may be positioned in contact with each of the semiconductor layers 127. A second dielectric layer may be positioned between upper and lower portions of the first dielectric layer. The dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials, Paras [0052], [0056], Figure 1A).
Lin discloses a structure that includes both the sidewall spacer 131 and the outer layer that is, the first dielectric layer. Lin teaches the possibility of the sidewall spacer 131 and the first dielectric layer being made of SiOCN.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to implement Lin’s teachings of wherein the gate spacer and the outer layer comprise SiBCN or SiOCN in the device of Qin it is merely using known materials to achieve a predictable optimization of device performance.
Regarding claim 6, Qin, as modified by Chan and Lin, teaches the limitations of claim 2 as mentioned above. Qin further teaches
wherein the upper inner spacer layer contacts the integrated insulator (see e.g., the upper gate spacer 106 contacts the dielectric layer 114, Figures 1B, 5A and 7A).
Qin does not explicitly teach
“the outer layer”
In a similar field of endeavor Chan teaches
an outer layer (see e.g., The middle insulating layer 120 may be formed of an insulating material, such as an oxide or a nitride. For example, the middle insulating layer 120 may comprise or be formed of SiO.sub.2, SiN, SiC, SiCN, SiOCN, SiOBCN or SiON. The middle insulating layer 120 may be formed as a composite layer structure comprising, e.g., a stack of two or more different insulating layers, Paras [0043], [0080], Figures 1B, 5A and 7B).
Chan’s middle insulating layer 120 has a multilayer structure, the outermost material layer being the outer layer could be formed of SiOCN.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to implement Chan’s teachings of outer layer in the device of Qin as the use of a multilayer dielectric structure is a known technique in semiconductor device manufacturing and is routinely employed to predictably optimize device performance.
Regarding claim 7, Qin, as modified by Chan and Lin, teaches the limitations of claim 2 as mentioned above. Qin does not explicitly teach
“wherein the upper inner spacer layer and the inner layer comprise a same material”.
In a similar field of endeavor Lin teaches
wherein the upper inner spacer layer and the inner layer comprise a same material (see e.g., The inner spacers 114 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials without departing from the scope of the present disclosure. In one example, the inner spacers 114 include silicon oxycarbonitride.
The dielectric layer 129 may include multiple layers of different dielectric material between the semiconductor layers 127. For example, a first dielectric layer may be positioned in contact with each of the semiconductor layers 127. A second dielectric layer may be positioned between upper and lower portions of the first dielectric layer. The dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials, Paras [0052], [0056], Figure 1A).
Lin discloses a structure that includes both the inner spacers 114 and the inner layer that is, the second dielectric layer. Lin teaches the possibility of the inner spacers 114 and the first dielectric layer being made of same material.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to implement Lin’s teachings of wherein the upper inner spacer layer and the inner layer comprise a same material in the device of Qin it is merely using known materials to achieve a predictable optimization of device performance.
Regarding claim 8, Qin, as modified by Chan and Lin, teaches the limitations of claim 2 as mentioned above. Qin further teaches
wherein the lower channel region comprises a plurality of lower channel regions, and (see e.g., the lower nanosheet transistor has a plurality of nanosheet channel layers 107, Para [0042], Figures 1B, 5A and 7A)
the lower transistor further comprises:
a lower source/drain region contacting the plurality of lower channel regions (see e.g., the lower nanosheet transistor comprises bottom source/drain region 111 contacting the lower nanosheet channel layers 107, Para [0044], Figures 1B, 5A and 7A);
a lower gate structure on the plurality of lower channel regions; and (see e.g., lower gate layers 105 on the plurality of nanosheet channel layers 107, Para [0043], Figures 1B, 5A and 7A)
a lower inner spacer layer that is between the lower source/drain region and the lower gate structure and is between the plurality of lower channel regions (see e.g., lower gate spacers 106 between the source/drain region 111 and the lower gate layers 105 and between the plurality of lower nanosheet channel layers 107, Para [0043], Figures 1B, 5A and 7A),
Qin does not explicitly teach
“wherein the lower inner spacer layer comprises a material different from the outer layer”.
In a similar field of endeavor
wherein the lower inner spacer layer comprises a material different from the outer layer (see e.g., The inner spacers 114 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials without departing from the scope of the present disclosure. In one example, the inner spacers 114 include silicon oxycarbonitride.
The dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials.
The dielectric layer 129 may include multiple layers of different dielectric material between the semiconductor layers 127. For example, a first dielectric layer of silicon oxide may be positioned in contact with each of the semiconductor layers 127. A second dielectric layer of silicon nitride may be positioned between upper and lower portions of the first dielectric layer, Paras [0040], [0052], [0056], Figure 1A).
Lin discloses a structure that includes both the inner spacers and the outer layer that is, the first dielectric layer. Lin discloses a specific example where the first dielectric layer is made of silicon oxide and the inner spacers 114 made of silicon oxycarbonitride, providing a clear example of different materials used for the inner spacers 114 and the first dielectric layer.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of wherein the lower inner spacer layer comprises a material different from the outer layer in the device of Qin as the use of a multilayer dielectric structure is a known technique in semiconductor device manufacturing and is routinely employed to predictably optimize device performance.
Regarding claim 9, Qin teaches an integrated circuit device (see e.g., Figures 1-7) comprising:
an upper transistor (see e.g., stacked transistor structure 100 includes an upper nanosheet transistor, Para [0041], Figures 1B, 5A and 7A) on a substrate (see e.g., upper nanosheet transistor disposed on substrate 101, Para [0039], Figures 1B, 5A and 7A), wherein the upper transistor comprises an upper channel region (see e.g., the upper nanosheet transistor comprises upper nanosheet channel layers 107, Para [0042], Figures 1B, 5A and 7A) and an upper gate electrode on the upper channel region (see e.g., upper gate layers 105 on the plurality of upper nanosheet channel layers 107, Para [0043], Figures 1B, 5A and 7A);
a lower transistor (see e.g., stacked transistor structure 100 includes a lower nanosheet transistor, Para [0041], Figures 1B, 5A and 7A) between the substrate and the upper transistor (see e.g., the lower nanosheet transistor is between the upper nanosheet transistor and the substrate 101, Figures 1B, 5A and 7A), wherein the lower transistor comprises a lower channel region (see e.g., the lower nanosheet transistor comprises nanosheet channel layers 107, Para [0042], Figures 1B, 5A and 7A) and a lower gate electrode on the lower channel region; and (see e.g., lower gate layers 105 on the plurality of lower nanosheet channel layers 107, Para [0043], Figures 1B, 5A and 7A)
an integrated insulator that is between the lower gate electrode and the upper gate electrode (see e.g., dielectric layer 114 separates the upper nanosheet transistor and the lower nanosheet transistor and is disposed between the lower and upper gate layers 105, Para [0041], Figures 1B, 5A and 7A)
Qin does not explicitly teach
“Integrated insulator……comprises an inner layer and an outer layer,
wherein the inner layer and the outer layer comprise different materials”,
In a similar field of endeavor Chan teaches
Integrated insulator……comprises an inner layer and an outer layer,
wherein the inner layer and the outer layer comprise different materials (see e.g., middle insulating layer 120 may be formed of an insulating material, such as an oxide or a nitride. For example, the middle insulating layer 120 may comprise or be formed of SiO.sub.2, SiN, SiC, SiCN, SiOCN, SiOBCN or SiON. The middle insulating layer 120 may be formed as a composite layer structure comprising, e.g., a stack of two or more different insulating layers, Para [0080], Figure 1),
Consequently, if the middle insulating layer 120 has a multilayer structure, the outermost material layer would be treated as the outer layer and any material layer situated beneath it would be the inner layer. As these layers are described as being made of different materials, the structure by its very nature comprises an outer and an inner layer of different materials.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chan’s teachings of Integrated insulator……comprises an inner layer and an outer layer, wherein the inner layer and the outer layer comprise different materials in the device of Qin as the use of a multilayer dielectric structure is a known technique in semiconductor device manufacturing and is routinely employed to predictably optimize device performance.
Qin does not explicitly teach
“the outer layer extends between the inner layer and the lower gate electrode and between the inner layer and the upper gate electrode, and wherein an upper surface of the lower gate electrode is higher than a lowermost end of the integrated insulator.”.
In a similar field of endeavor Lin teaches
the outer layer extends between the inner layer and the lower gate electrode and between the inner layer and the upper gate electrode (see e.g., The dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials.
The dielectric layer 129 may include multiple layers of different dielectric material between the semiconductor layers 127. For example, a first dielectric layer may be positioned in contact with each of the semiconductor layers 127. A second dielectric layer may be positioned between upper and lower portions of the first dielectric layer, Paras [0040], [0052], [0056], Figure 1A).
Lin discloses an outer layer that is, the first dielectric layer and an inner layer that is, the second dielectric layer. The first dielectric layer extends between the second dielectric layer and the lower gate metal 113 and between the second dielectric layer and the upper gate metal 112.
wherein an upper surface of the lower gate electrode is higher than a lowermost end of the integrated insulator (see e.g., the gate metals 112 and 113 meet at an interface 139. The dielectric layer 129 has a top surface 135 and a bottom surface 137. The interface 139 is lower than a top surface 135 and higher than a bottom surface 137 of the dielectric layer 129. As shown in Figure 1B the interface 139 (that is, upper surface of the lower gate electrode) is higher than the bottom surface 137 of the dielectric layer 129, Para [0054])
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of the outer layer extends between the inner layer and the lower gate electrode and between the inner layer and the upper gate electrode, wherein an upper surface of the lower gate electrode is higher than a lowermost end of the integrated insulator and wherein an upper surface of the lower gate electrode is higher than a lowermost end of the integrated insulator in the device of Qin as the use of a multilayer dielectric structure is a known technique in semiconductor device manufacturing and is routinely employed to predictably optimize device performance and the specific structural relationship between the lower gate electrode and the dielectric layer ensures that there is no work function interference of the upper transistor with the gate metal of the lower transistor.
Regarding claim 10, Qin, as modified by Chan and Lin, teaches the limitations of claim 9 as mentioned above. Qin does not explicitly teach
“wherein an upper portion of the integrated insulator is above an interface where the upper gate electrode contacts the lower gate electrode and a lower portion of the integrated insulator is below the interface”.
In a similar field of endeavor Lin teaches
wherein an upper portion of the integrated insulator is above an interface where the upper gate electrode contacts the lower gate electrode and a lower portion of the integrated insulator is below the interface (see e.g., the gate metals 112 and 113 meet at an interface 139. The dielectric layer 129 has a top surface 135 and a bottom surface 137. The interface 139 is lower than a top surface 135 and higher than a bottom surface 137 of the dielectric layer 129. As shown in Figure 1B the upper portion of the dielectric layer 129 is above the interface 139 and a lower portion of the dielectric layer 129 is below the interface 139, Para [0054])
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of wherein an upper portion of the integrated insulator is above an interface where the upper gate electrode contacts the lower gate electrode and a lower portion of the integrated insulator is below the interface in the device of Qin in order to improve device performance and to ensure that there is no work function interference of the upper transistor with the gate metal of the lower transistor.
Regarding claim 11, Qin, as modified by Chan and Lin, teaches the limitations of claim 9 as mentioned above. Qin does not explicitly teach
wherein the upper surface of the lower gate electrode is lower than an uppermost end of the integrated insulator (see e.g., upper surface of the lower gate layer 105 is lower than an uppermost end of dielectric layer 114, Figures 1A, 5A and 7B).
Regarding claim 12, Qin, as modified by Chan and Lin, teaches the limitations of claim 9 as mentioned above. Qin does not explicitly teach
“wherein the outer layer encloses the inner layer”.
In a similar field of endeavor Lin teaches
wherein the outer layer encloses the inner layer (see e.g., The dielectric layer 129 may include multiple layers of different dielectric material between the semiconductor layers 127. For example, a first dielectric layer may be positioned in contact with each of the semiconductor layers 127. A second dielectric layer may be positioned between upper and lower portions of the first dielectric layer; hence the second dielectric layer is enclosed by the first dielectric layer, Paras [0056], [0078], Figure 1A).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of wherein the outer layer encloses the inner layer in the device of Qin as the use of a multilayer dielectric structure is a known technique in semiconductor device manufacturing and is routinely employed to predictably optimize device performance.
Regarding claim 13, Qin, as modified by Chan and Lin, teaches the limitations of claim 12 as mentioned above. Qin does not explicitly teach
“wherein the outer layer has a uniform thickness along a surface of the inner layer”.
In a similar field of endeavor Lin teaches forming a first dielectric layer encapsulating the second dielectric layer.
In semiconductor fabrication a standard process for creating dielectric films is Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD) or similar techniques. These processes deposit materials in a highly conformal and uniform manner over underlying structures.
Therefore, when a second dielectric layer is deposited and then encapsulated by the first dielectric layer the result is a unform thickness outer layer surrounding the inner layer.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to have the outer layer a uniform thickness along a surface of the inner layer as uniformity is the standard and predictable result of most deposition processes to form such layers. A uniform outer layer is necessary for consistent electrical performance across the device. Variations in thickness would lead to variations in electrical properties which is generally undesirable for device reliability and performance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893