Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to response to application 18/185042 filed on 03/16/23.
Summary of claims
Claims 1-9 are pending.
Claims 1-9 are rejected.
Oath/Declaration
The oath/declaration filed on March 16th, 2023 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishander et al. (US Pub. 2016/0171136).
As to claims 1 the prior art teaches a method for generating optimal sizing solutions for devices of an analog circuit (see fig 1) that satisfy the design specifications on circuit performance parameters and robustness parameters, wherein at each iteration of determining the optimal sizing solution, prediction models are trained and optimization is executed on the prediction models, and the iteration stops when a qualified solution is found or a preset maximum number of iterations is reached, wherein an ensemble of classifier chain models is trained to predict each target circuit performance parameter based on device sizes by training on circuit data (see fig 1 -8 paragraph 0020-0035 and 0129-0140).
As to claims 2, the prior art teaches wherein a multi-objective genetic algorithm is executed on m ensembles of the classifier chain to simultaneously maximize a probability that each of m performance specifications are satisfied (see fig 8-12 and 0302-0326).
As to claims 3 the prior art teaches wherein the performance specifications of an analog circuit are generated with a SPICE solver that randomly generates combinations of transistor sizes; then binary labels are assigned with a classification with an algorithm that adaptively sets labeling thresholds (see fig 8-13 and 0326-0344).
As to claims 4 the prior art teaches wherein classification is performed while using the algorithm, wherein a threshold is specified on a percentile of data values of a performance parameter to resolve lass imbalance in a sampled dataset; wherein if the percentile value exceeds a specification value of the performance parameter, the threshold is set to a specification value (see fig 8-14 paragraph 0341-0366).
As to claim 5 the prior art teaches wherein binary labels are assigned as reference to the threshold (see fig 8-16 paragraph 0380-0412).
As to claims 6 the prior art teaches wherein 1 is assigned for qualified data points and 0 is assigned for unqualified data points (see fig 8-16 paragraph 0414-0437).
As to claims 7 the prior art teaches wherein one ensemble model is comprised of a number of decision-tree classifiers and a final prediction of the ensemble is calculated as an average of the predictions of all the classifiers (see fig 1 -8 paragraph 0020-0035 and 0145-0165).
As to claims 8 the prior art teaches wherein to account for effects of circuit variations on circuit performance, standard deviations are calculated on evaluations of a performance parameter at all process, voltage, and temperature corners considered in an application of a set of transistor sizes (see fig 1 -8 paragraph 0160-0180).
As to claim 9 the prior art teaches a method for sizing analog circuit components using a simulation-based optimization framework using classifier chains that represent relationships among output parameters to improve framework accuracy, wherein when considering effects of design variations on circuit performance, simulations for each design point are acquired at each corner of interest and the standard deviations of the performance variations across all of the corners for each design point are then calculated, wherein design points with performance fluctuations that fall below a set threshold T thre of the standard deviation are assigned with positive labels, while all other points are assigned negative labels (see fig 1 -9 paragraph 0020-0037 and 0141-0154).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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