DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11611276. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims recite similar limitations in the application claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Walimbe et al. (US 6552600) in view of Lee et al. (US 6023188) and Sagisaka et al. (US 7855588).
As to claim 1, Walimbe et al.’s figures 2 and 3 show a charge pump circuit, comprising: input and output nodes (input of the first pump stage 26a and output of final pump stage 26n); an output stage circuit (final pump stage) coupled to the output node; a pumping stage circuit (1st pump stage) coupled between the input node and the output stage circuit; and a control circuit (21-23) configured to output first and second control signals (CLK2 and CLK1 or inputs of drivers in 23 that provides CLK1 and CLK2) to respective first and second control signal terminals of the pumping stage circuit. Figure 3 shows an internal structure of each pump stage circuit. Figure 3 fails to show the clock signals applied to the pump stage as claimed. However, Lee et al.’s figure 6B and 6C shows a similar and precise plump stage and Sagisaka et al.’s figure 1 shows a clock generator that is compatible with Lee et al.’s pump stage. Therefore, it would have been obvious to one having ordinary skill in the art to use Lee et al.’s pump stage and Sagisaka et al.’s clock generator for at least one of Walimbe et al.’s pump stage and clock generator for the purpose of providing more precise pumped voltage (further see Lee et al.’s figure 6A for various stages receiving various clock signals). Thus, the modified Walimbe et al.’s figures further show that the pumping stage circuit comprises: a first input terminal (Walimbe’s input 11 or Lee et al.’s Source); an output terminal (Walimbe’s output 13 or Lee et al.’s Drain); a first transistor (Lee’s M1 or M4 in figure 6A) comprising a first source/drain (S/D) terminal coupled to the first input terminal, a second S/D terminal coupled to the output terminal, and a first gate terminal; a first capacitive device (Lee et al.’s C1A or C4A) coupled between the first control signal terminal and the first gate terminal; a second capacitive device (Lee et al.’s C1 or C4) coupled between the second control signal terminal and the second S/D terminal; a first diode device (Lee et al.’s M1B or M4B) comprising a first anode coupled to the first gate terminal and a first cathode coupled to the second S/D terminal; and a second diode device (Lee et al.’s M1A or M4A) comprising a second cathode coupled to the first gate terminal and a second anode coupled to the second S/D terminal, the output stage circuit comprises: a second input terminal; and a second transistor (Lee’s M1 in the final stage) comprising a third S/D terminal coupled to the second input terminal and a fourth S/D terminal coupled to the output node, wherein the control circuit is configured to generate each of the first control signal (Lee’s /F2 or Sagiaka’s /Y) and the second control signal (Lee et al.’s F1 or Sagisaka X) having the same operation cycle (see Lee et al.’s figures 6C and 6E), wherein the first control signal and the second control signal comprises: a first transition from a logic low level to logic high level (positive edge) and a second transition from the logic high level to the logic low level (negative edge) during a first portion of an operation cycle (half period); and the logic low level during a remainder of the operating cycle (another half period), generate the first control signal (Lee et al.’s /F2) comprising the first transition at a first time and the second control signal (Lee et al.’s F1) comprising the first transition a second time subsequent the first time. The figures fail to show that the time period between the first transition in the first control signal and the first transition in the second control signal is sufficiently small to cause a change in a voltage at the second S/D terminal of the first transistor from the first time to the second time to be less than 100 millivolts. However, it is known that the output voltage amplitude swing dependents on the amplitude, phases and/or frequency of the clock signals (Lee’s F1 and F2 or Sagisa’s X and Y). Sagisaka et al.’s figure 1 suggests that the phases of signals X and Y are adjustable by controlling delay circuits 1a and 1b. Therefore, it would have been obvious to one having ordinary skill in the art to select the clock frequency (clock frequency relates to the time between the first and second transitions which is about ½ the wavelength of the signals), voltage amplitudes, clock phases and/or component sizes such that a change in a voltage at the second S/D terminal of the first transistor from the first time to the second time to be less than 100 millivolts in order to achieve optimum performance, see MPEP 2144.05.
As to claim 2, the modified Walimbe et al.’s figures show that another time period between the second transition in the second control signal at a third time and the second transition in the first control signal at a fourth time subsequent to the third time is sufficiently small to cause another change in the voltage at the second S/D terminal of the first transistor from the third time to the fourth time to be less than 100 millivolts.
Claim 17 recites similar limitations in claims above. Therefore, it is rejected for the same reasons.
Claim(s) 3-7, 9, 11-15 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Walimbe et al. (US 6552600) in view of Lee et al. (US 6023188), Sagisaka et al. (US 7855588) and Ganesan et al. (US 6297974).
As to claim 3, Walimbe et al.’s figures fail to show that a forward bias voltage drop of the first diode device is greater than a forward bias voltage drop of the second diode device. However, Ganesan et al.’s figure 6 shows a similar circuit that a forward voltage of first diode 625 is greater than forward voltage drop of second diode 621 (Col. 7, lines 45-65). It would have been obvious to one having ordinary skill in the art to select the forward volage drop of Walimbe et al. or Lee et al.’s first diode to be greater than the forward voltage drop of the second diode for the purpose of achieving optimum output amplitude.
As to claim 4, since the forward voltage drop of the first diode is greater than the forward voltage drop of the second diode, it would have been obvious to one having ordinary skill in the art to select the forward bias voltage drop of the first diode device to be greater than a threshold voltage of the first transistor in order to achieve optimum output amplitude.
As to claim 5, selecting the forward bias voltage drop of the first diode device to be less than a voltage difference between the logic low level and the logic high level is seen as an obvious design preference to ensure optimum performance, see MPEP 2144.05, i.e., the clock amplitude is about 3V (Walimbe’s col. 1, line 21) and the transistor threshold normally about 0.4-0.7 V.
As to claim 6, a diode formed by plurality of series connected diodes is well known in the art. It would have been obvious to one having ordinary skill in the art to select plurality of series connected diodes for at least one of the first and second diodes for the purpose of achieving desired forward voltage drop. Thus, the modified figures show that one or both of the first or second diode devices comprises a plurality of diode-connected transistors coupled in series.
As to claim 7, Walimbe et al.’s figure 2 shows that circuit 23 comprises plurality of clock drives. Therefore, Walimbe et al.’s figures show the pumping stage circuit further comprises: a first driver (not shown the provide Lee’s /F2) coupled between the first control signal terminal and the first capacitive device; and a second driver (not shown that Lee’s F1) coupled between the second control signal terminal and the second capacitive device (further see Sagisaka’s clock generator).
Claims 9 recites similar limitations in claims above. Therefore, it is rejected for the same reasons.
As to claim 11, drive comprising inverter, buffer or level shifter is well known in the art. It would have been obvious to one having ordinary skill in the art to use inverter, buffer or level shifter for the first and or second drivers for the purpose of saving space, reducing noise or achieving optimum clock amplitudes.
As to claim 12, the modified Walimbe et al.’s figures show that the control circuit is configured to generate the first control signal and the first driver is configured to output the first driving signal each having a first voltage level corresponding to the first or second logic level being a logic high level, the control circuit is configured to generate the second control signal and the second driver is configured to output the second driving signal each having a second voltage level corresponding to the first or second logic level being the logic high level, and the first voltage level is greater than the second voltage level.
As to claim 13, the modified Walimbe et al.’s figures show that the control circuit is configured to generate each of the first and second control signals having a first voltage level corresponding to the first or second logic level being a logic high level, the first and second drivers are configured to output each of the respective first and second driving signals having a second voltage level corresponding to the first or second logic level being the logic high level, and the first voltage level is greater than the second voltage level.
Claim 14 recites similar limitations of claims above. Therefore, it is rejected for the same reasons.
As to claim 15, Walimbe et al.’s figures shows that the control circuit is configured to generate the first and second control signal based on a clock signal, see Sagisaka et al.’s figure 1)
Claims 19-20 recite similar limitations in claims above. Therefore, they are rejected for the same reasons.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Walimbe et al. (US 6552600) in view of Lee et al. (US 6023188), Sagisaka et al. (US 7855588) and Yajima et al. (US 20130321069).
As to claim 8, the modified Walimbe et al.’s figures show that the output stage circuit (final stage) further comprises: a third control signal terminal configured to receive the first control signal; a third capacitive device (C1A in the final stage) coupled between the third control signal terminal and a second gate terminal of the second transistor. The figures fail to show a fourth capacitive device coupled between the output node and a supply reference terminal configured to have a voltage level the same as the logic low level. However, Yajima et al.’s figure 11 shows a charge pump circuit that comprises capacitor C95 coupled between output node and ground in order to provide stable output voltage. Therefore, it would have been obvious to one having ordinary skill in the art to add a capacitor coupled between Walimabe’s output node and ground for the purpose of providing more stable output voltage. The modified Walimbe’s figures further show a third diode device (M1B) comprising a third anode coupled to the second gate terminal and a third cathode coupled to the fourth S/D terminal; and a fourth diode device (M1A) comprising a fourth cathode coupled to the second gate terminal and a fourth anode coupled to the fourth S/D terminal.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Walimbe et al. (US 6552600) in view of Lee et al. (US 6023188), Sagisaka et al. (US 7855588), Ganesan et al. (US 6297974) and Yajima et al. (US 20130321069).
The modified Walimbe et al.’s figures show that the output stage circuit (final stage) further comprises: a third control signal terminal configured to receive the first control signal; a third capacitive device (C2 in the final stage) coupled between the third control signal terminal and a second gate terminal of the second transistor. The figures fail to show a fourth capacitive device coupled between the output node and a supply reference terminal configured to have a voltage level the same as the logic low level. However, Yajima et al.’s figure 11 shows a charge pump circuit that comprises capacitor C95 coupled between output node and ground in order to provide stable output voltage. Therefore, it would have been obvious to one having ordinary skill in the art to add a capacitor coupled between Walimabe’s output node and ground for the purpose of providing more stable output voltage. The modified Walimbe’s figures further show a third diode device (Lee’s M1B) comprising a third anode coupled to the second gate terminal and a third cathode coupled to the fourth S/D terminal; and a fourth diode device (Lee’s M1A) comprising a fourth cathode coupled to the second gate terminal and a fourth anode coupled to the fourth S/D terminal.
Conclusion
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/QUAN TRA/
Primary Examiner
Art Unit 2842