Prosecution Insights
Last updated: April 18, 2026
Application No. 18/185,500

MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE

Non-Final OA §102§103
Filed
Mar 17, 2023
Examiner
HOSSAIN, KAZI S
Art Unit
2837
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
VIA LABS, INC.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
96%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
485 granted / 610 resolved
+11.5% vs TC avg
Strong +16% interview lift
Without
With
+16.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
34 currently pending
Career history
644
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
66.6%
+26.6% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
5.9%
-34.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 610 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Elections/Restrictions Applicant’s election of Species 2 (Figs. 2-4; Claims 1-9 and 11-15) in the reply filed on 03/05/2026 is acknowledged. However, since applicant did not distinctly indicate whether election is with or without traverse and did not point out any supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a) and 818.03(c)). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 2. Claims 1-3 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Valentin (US 20170287623 A1). Regarding Claim 1: Valentin teaches that a multilayer-type on-chip inductor structure, comprising: an inter-metal dielectric (IMD) layer (i.e. upper, intermediate and lower layer formed the IMD layer in Fig. 2; para 0045--053) having an inductor central region (i.e. central region “O” in Fig. 2); a first metal winding portion (1011) disposed in the IMD layer, comprising: a first spiral-type coil (113) surrounding the inductor central region; and a first open ring-type coil (101) surrounding the first spiral-type coil; and a second metal winding portion (1101)disposed in the IMD layer and electrically connected to the overlying first metal winding portion, comprising: a second spiral-type coil (110) vertically overlapping (construed from Fig. 2) the first spiral-type coil and the first open ring-type coil, so that an outermost-turn coil (i.e. outer part of coil 110 in Fig. 2) of the second spiral-type coil corresponds to the first open ring-type coil. Regarding Claim 2: As applied to claim 1, Valentin teaches that a first via-structure region (111) disposed between the first open ring-type coil and the outermost-turn coil of the second spiral-type coil (construed from Fig. 2), so that the first open ring-type coil is electrically connected to the second spiral-type coil; and a second via-structure region (109) disposed between an outermost-turn coil of the first spiral-type coil and an innermost-turn coil of the second spiral-type coil, so that the first spiral-type coil is electrically connected to the second spiral-type coil. Regarding Claim 3: As applied to claim 1, Valentin teaches that the second metal winding portion further comprises: a second open ring-type coil (116, Fig. 2) vertically overlapping an innermost-turn coil of the first spiral-type coil. Regarding Claim 9: As applied to claim 1, Valentin teaches that the first metal winding portion is defined by a topmost metal layer (i.e. upper layer in Fig. 2) in the IMD layer, and the second metal winding portion is defined by a next-topmost metal layer (i.e. intermediate layer in Fig. 2) in the IMD layer. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4 and 5 are rejected under AIA 35 U.S.C. 103 as obvious over by Valentin. Regarding Claim 4: As applied to claim 1, Valentin teaches that a first via-structure region (111) disposed between the first open ring-type coil and the outermost-turn coil of the second spiral-type coil (construed from Fig. 2), so that the first open ring-type coil is electrically connected to the second spiral-type coil; and a second via-structure region (109) disposed between an outermost-turn coil of the first spiral-type coil and an innermost-turn coil of the second spiral-type coil, so that the first spiral-type coil is electrically connected to the second spiral-type coil except a third via-structure region disposed between the innermost-turn coil of the first spiral-type coil and the second spiral-type coil, so that the first spiral-type coil is electrically connected to the second open ring-type coil. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a third via-structure region disposed between the innermost-turn coil of the first spiral-type coil and the second spiral-type coil, so that the first spiral-type coil is electrically connected to the second open ring-type coil, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. MPEP 2144.04 (VI-B), It is noted that in the instant application, para 0007, applicant has not disclosed any criticality for the claimed limitations. Regarding Claim 5: As applied to claim 1, Valentin does not teaches that the first spiral-type coil and the second spiral-type coil are spiral-type coils with a same number of turns. Nevertheless, Valentin discloses in another embodiment (in Fig. 4) that the first spiral-type coil (304) and the second spiral-type coil (310) are spiral-type coils with a same number of turns (construed from Fig. 4). Thus, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate (from embodiment of Fig. 4) the first spiral-type coil and the second spiral-type coil are spiral-type coils with a same number of turns (into embodiment of fig. 2) such that the combination teaches the first spiral-type coil and the second spiral-type coil are spiral-type coils with a same number of turns. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the first spiral-type coil and the second spiral-type coil are spiral-type coils with a same number of turns as claimed to meet design requirements for certain applications. Allowable Subject Matter Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 6 recites, a first output/input portion and a second output/input portion disposed in the IMD layer outside the first open ring-type coil, wherein the first output/input portion extends to an end portion of the first open ring-type coil, and wherein the second output/input portion is physically separated from the first open ring-type coil. Claims 11-15 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Claim 11 recites, A multilayer-type on-chip inductor structure, comprising: an inter-metal dielectric (IMD) layer having an inductor central region; a topmost metal layer disposed in the IMD layer, comprising: a first double-turn spiral-type coil surrounding the inductor central region; and a first single-turn open ring-type coil surrounding the first double-turn spiral-type coil; a next-topmost metal layer disposed in the IMD layer, comprising: a second single-turn open ring-type coil surrounding the inductor central region and vertically overlapping an inner-turn coil of the first double-turn spiral-type coil; and a second double-turn spiral-type coil surrounding the second single-turn open ring-type coil, wherein the first single-turn open ring-type coil vertically overlaps an outer-turn of the second double-turn spiral-type coil; and a first via-structure region, a second via-structure region, and a third via-structure region disposed between the topmost metal layer and the next-topmost metal layer and electrically connected thereto. The references of record do not teach or suggest the aforementioned limitations, nor would it be obvious to modify those references to include such limitations. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. A list of pertinent prior art is attached in form 892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kazi Hossain whose telephone number is 571-272-8182. The examiner can normally be reached on Monday-Thursday from Monday to Thursday 8:00 AM to 4:30 PM (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https:/www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Shawki Ismail can be reached on 571-272-3985. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https:/www.uspto.gov/patents/apply/patent- center for more information about Patent Center and https:/www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KAZI HOSSAIN/ Examiner, Art Unit 2837 /SHAWKI S ISMAIL/Supervisory Patent Examiner, Art Unit 2837
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Prosecution Timeline

Mar 17, 2023
Application Filed
Mar 26, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

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2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
96%
With Interview (+16.3%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 610 resolved cases by this examiner. Grant probability derived from career allow rate.

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