Prosecution Insights
Last updated: October 04, 2026

VIA LABS, INC.

Technology area: Semiconductors, Circuits & Optics

3 pending office actions • 2 art units • 3 examiners • 0 of 3 (0%) have an AI response strategy ready • 5 patents granted in the last 365 days

Analysis

VIA LABS, INC. currently manages 3 pending office actions within the Semiconductors, Circuits & Optics technology area. These 3 actions are distributed among 3 distinct examiners, meaning each pending application is being reviewed by a different person. These examiners are located across 2 distinct art units, indicating some level of technical overlap in the administrative handling of the applications. This distribution suggests that while the examiners are different, the technical subject matter is concentrated in a few areas.

YALDO, ABIGAIL AMIR is the busiest examiner for the company, responsible for 1 pending office action. Because there are distinct examiners for the pending actions, the workload is spread evenly, with no single examiner handling more than 1 case. The use of 2 distinct art units suggests that at least some of the examiners are likely working within the same technical group, even though they are distinct individuals. This requires the company to monitor the specific habits of the different examiners while navigating the standards of the art units.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Portfolio Summary

3
Total Pending OAs
2
Non-Final OAs
1
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 2 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

0
Overdue
1
Due this week
0
Due this month
1
Due in next 60 days
0
Due later

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

3
Hard (100%)
0
Medium (0%)
0
Easy (0%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
Multi-statute (no §101)3 (100%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
0
Information Tech
0% of docket
0
Communications
0% of docket
2
Semiconductors
67% of docket
0
Mechanical / Eng
0% of docket
1
Business / Other
33% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

30 h
Manual time on pending OAs
6 h
Time saved (low, 20%)
10 h
Time saved (mid, 35%)
0.3 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
YALDO, ABIGAIL AMIR 1 93.7% +17.4%
BELLIDO, NICOLAS G 1 89.1% +12.9%
HOSSAIN, KAZI S 1 80.0% +16.0%

Hard Cases (3)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.

App #TitleExaminerDue in
18671921 INTEGRATED CIRCUIT CAPABLE OF WITHSTANDING ELECTRICAL OVER STRESS BELLIDO, NICOLAS G 7d
18185500 MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE HOSSAIN, KAZI S 40d
19189371 ELECTRONIC DEVICE YALDO, ABIGAIL AMIR —

Interview Candidates (3)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 3 ordered by deadline are shown.

App #TitleExaminerDue in
18671921 INTEGRATED CIRCUIT CAPABLE OF WITHSTANDING ELECTRICAL OVER STRESS BELLIDO, NICOLAS G 7d
18185500 MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE HOSSAIN, KAZI S 40d
19189371 ELECTRONIC DEVICE YALDO, ABIGAIL AMIR —

Top Art Units

Art UnitApps
2838 1
2837 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
19189371 ELECTRONIC DEVICE YALDO, ABIGAIL AMIR — §103§112 Non-Final OA — Pending Apr 25, 2025
18671921 INTEGRATED CIRCUIT CAPABLE OF WITHSTANDING ELECTRICAL OVER STRESS BELLIDO, NICOLAS G 2838 §102§103 Non-Final OA 7d Pending May 22, 2024
18185500 MULTILAYER-TYPE ON-CHIP INDUCTOR STRUCTURE HOSSAIN, KAZI S 2837 §102§103 Final Rejection 40d Pending Mar 17, 2023

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