DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on December 16, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3, 5, 8-9, 13-15, 17, and 20-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As to claims 1 and 13, the limitation “a field oxide, a metal layer, a main junction, and a passivation layer that are sequentially stacked on a semiconductor substrate” is not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Specifically, as explicitly disclosed in [0057] of the Specification, “the power semiconductor chip includes a main junction 14, a field oxide 12, an metal layer 11, and a passivation layer 13 that are sequentially stacked on the semiconductor substrate 10.” It is clear such a sequential order is from the semiconductor substrate having the main junction 14 to the topmost element of the passivation layer 13. Thus, the recited sequential stack is not described in the Specification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5, 8-9, 13-15, 17, and 20-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claims 1 and 13, the limitation “a field oxide, a metal layer, a main junction, and a passivation layer that are sequentially stacked on a semiconductor substrate” fails to specify whether the limitation “sequentially stacked” does not necessarily indicate any particular order. As discussed above, the disclosed main junction is actually below the field oxide followed by the metal layer and the passivation layer. It is not clear whether the limitation “main junction” is interpreted as the interface/junction between the metal layer and the passivation layer such that the sequential order is from the field oxide, the metal layer, the main junction that is the interface between the metal layer and the passivation layer, and lastly the passivation layer. Thus, the limitation renders the claims indefinite and clarification is required. As to claim 9, the limitation “a side of the another metal layer facing away from the semiconductor substrate to a side of the another metal layer that is adjacent to the another metal layer and that faces away from the semiconductor substrate” fails to clearly define the “side”. It is noted that “a side of the another metal layer” is recited multiple times. It is also not clear what “a side of the another metal layer that is adjacent to the another metal layer” is directed to as the side is already a part of the another metal layer. Thus, the limitation renders the claim indefinite and clarification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 5, 8-9, 13-15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0127082 A1 to Chen et al. (“Chen”) in view of U.S. Patent Application Publication No. 2017/0317068 A1 to Kaneda (“Kaneda”) and U.S. Patent Application Publication No. 2002/0190340 A1 to Moriguchi et al. (“Moriguchi”).
As to claim 1, Chen in view of Kaneda and Moriguchi discloses a chip (Kaneda ¶ 0026 and Moriguchi 40), divided into a main functional area (1), a transition area (3), and a protection area (2), wherein the transition area (3) is located between the main functional area (1) and the protection area (2); the chip comprises a field oxide (9, 108), a metal layer (8), a main junction (5, 7, 6, 115, interface between 8 and 13), and a passivation layer (13, 114) that are sequentially stacked on a semiconductor substrate (4), wherein the field oxide (9, 108) and the passivation layer (13, 114) are located in the transition area (3) and the protection area (2), and the metal layer (8) is located in the main functional area (1) and the transition area (3); in the transition area (3), the field oxide (9, 108) comprises a primary field oxide (9, 108 right) and at least one secondary field oxide (9, 108 left) that are disposed at intervals, wherein the secondary field oxide (9, 108 left) is located on a side of the primary field oxide (9, 108 right) facing the main functional area (1), the metal layer (8) extends from the main functional area (1) to a side of the primary field oxide (9, 108 right) facing away from the semiconductor substrate (4), and the passivation layer (13, 114) extends from a side of the metal layer (8) facing away from the semiconductor substrate (4) to a side of the metal layer (8) facing away from the main functional area (1); and wherein the main junction (5, 7, 6, 115, interface between 8 and 13) extends from the main functional area (1) to the protection area (2) and is in contact with the at least one secondary field oxide (9, 108 left), the primary field oxide (9, 108 right) and at least a part of the field oxide (9, 108) in the protection area (2) (See Fig. 1, Fig. 6, ¶ 0036-¶ 0041, ¶ 0071) (Notes: the protection area screens electrical influence on the interior. The limitation “main junction” is interpreted as an interface formed between two elements as the “junction” is not particularly specified. Lastly, Kaneda discloses the interlayer insulating film 62 is commonly formed of an oxide film in ¶ 0051). Although Chen does not specify the chip and the interlayer insulating film (108) is an oxide, Kaneda and Moriguchi disclose it is common the chip is divided into the main functional area, the transition area, and the protection area surrounding and protecting the main functional area and Kaneda further discloses the interlayer insulating film is commonly formed of the field oxide. As to claim 2, Chen further discloses wherein in the transition area (3), the passivation layer (13, 114) further extends from the side of the metal layer (8) facing away from the main functional area (1) to a side of the primary field oxide (9, 108 right) facing away from the main functional area (1); and the metal layer (8) covers a part of a surface on the side of the primary field oxide (9, 108 right) facing away from the semiconductor substrate (4), and the passivation layer (13, 114) extends from the side of the metal layer (8) facing away from the semiconductor substrate (4) through the side of the primary field oxide (9, 108 right) facing away from the semiconductor substrate (4) to the side of the primary field oxide (9, 108 right) facing away from the main functional area (1) (See Fig. 1). As to claim 3, Chen in view of Kaneda further discloses wherein there are a plurality of secondary field oxides (9, 108 left), and the plurality of secondary field oxides (9, 108 left) are disposed at intervals (See Chen Fig. 1 and Kaneda).
As to claim 5, Chen further discloses wherein the metal layer (8) comprises a first part (on 14) and a second part (on 9), the first part (on 14) is located in at least the main functional area (1), and the second part (on 9) is located in the transition area (3); and along a direction from the metal layer (8) to the semiconductor substrate (4), thickness of the first part (on 14) is greater than thickness of the second part (on 9) (See Fig. 1). As to claim 8, it would have been obvious Chen in view of Kaneda discloses wherein a thickness range of the first part (on 14) is [1 µm, 7 µm], and a thickness range of the second part (on 9) is [0.1 µm, 4 µm] as the thickness of the metal layer is about twice thick of the field oxide that is about 0.6 µm (See Kaneda Fig. 4, Fig. 5, Fig. 6, ¶ 0051). It would have been obvious to one of ordinary skill in the art to adjust the relative thicknesses in view of device properties and constraints such that a thicker metal layer may provide a lower resistance but a larger device size. As to claim 9, Chen further discloses wherein the chip further comprises another metal layer (8B) located in the protection area (2); and in the protection area (2), the another metal layer (8B) extends from the side of the primary field oxide (9, 108 right) facing away from the semiconductor substrate (4) to a side of the primary field oxide (9, 108 right) that is adjacent to the primary field oxide (9, 108 right) and that faces away from the semiconductor substrate (4), and the passivation layer (13, 114) extends from a side of the another metal layer (8B) facing away from the semiconductor substrate (4) to a side of the another metal layer (8B) that is adjacent to the another metal layer (8B) and that faces away from the semiconductor substrate (4) (See Fig. 1). As to claim 13, Chen in view of Kaneda and Moriguchi discloses an electronic device, comprising a circuit card (31, 71) and a chip (Kaneda ¶ 0026 and Moriguchi 40), wherein the chip (Kaneda ¶ 0026 and Moriguchi 40) is disposed on the circuit card (31, 71) and the chip (Kaneda ¶ 0026 and Moriguchi 40) is divided into a main functional area (1), a transition area (3), and a protection area (2), wherein the transition area (3) is located between the main functional area (1) and the protection area (2); the chip (Kaneda ¶ 0026 and Moriguchi 40) comprises a field oxide (9, 108), a metal layer (8), a main junction (5, 7, 6, 115, interface between 8 and 13), and a passivation layer (13, 114) that are sequentially stacked on a semiconductor substrate (4), wherein the field oxide (9, 108) and the passivation layer (13, 114) are located in the transition area (3) and the protection area (2), and the metal layer (8) is located in the main functional area (1) and the transition area (3); in the transition area (3), the field oxide (9, 108) comprises a primary field oxide (9, 108 right) and at least one secondary field oxide (9, 108 left) that are disposed at intervals, wherein the secondary field oxide (9, 108 left) is located on a side of the primary field oxide (9, 108 right) facing the main functional area (1), the metal layer (8) extends from the main functional area (1) to a side of the primary field oxide (9, 108 right) facing away from the semiconductor substrate (4), and the passivation layer (13, 114) extends from a side of the metal layer (8) facing away from the semiconductor substrate (4) to a side of the metal layer (8) facing away from the main functional area (1); and wherein the main junction (5, 7, 6, 115, interface between 8 and 13) extends from the main functional area (1) to the protection area (2) and is in contact with the at least one secondary field oxide (9, 108 left), the primary field oxide (9, 108 right) and at least a part of the field oxide (9, 108) in the protection area (2) (See Chen Fig. 1, Fig. 6, ¶ 0036-¶ 0041, ¶ 0071) (Notes: the protection area screens electrical influence on the interior. The limitation “main junction” is interpreted as an interface formed between two elements as the “junction” is not particularly specified. Lastly, Kaneda discloses the interlayer insulating film 62 is commonly formed of an oxide film in ¶ 0051. Furthermore, See Moriguchi Fig. 5, Fig. 9, Fig. 11, where the limitation “circuit card” is interpreted as a support to provide connections to the chip such that the chip is integrated that is well-known in semiconductor devices). Although Chen does not specify the circuit card, the chip, and the interlayer insulating film (108) is an oxide, Kaneda and Moriguchi disclose it is common the chip is provided on the circuit card in an integrated device and divided into the main functional area, the transition area, and the protection area surrounding and protecting the main functional area and Kaneda further discloses the interlayer insulating film is commonly formed of the field oxide. As to claim 14, Chen further discloses wherein in the transition area (3), the passivation layer (13, 114) further extends from the side of the metal layer (8) facing away from the main functional area (1) to a side of the primary field oxide (9, 108 right) facing away from the main functional area (1); and the metal layer (8) covers a part of a surface on the side of the primary field oxide (9, 108 right) facing away from the semiconductor substrate (4), and the passivation layer (13, 114) extends from the side of the metal layer (8) facing away from the semiconductor substrate (4) through the side of the primary field oxide (9, 108 right) facing away from the semiconductor substrate (4) to the side of the primary field oxide (9, 108 right) facing away from the main functional area (1) (See Fig. 1). As to claim 15, Chen in view of Kaneda further discloses wherein there are a plurality of secondary field oxides (9, 108 left), and the plurality of secondary field oxides (9, 108 left) are disposed at intervals (See Chen Fig. 1 and Kaneda). As to claim 17, Chen further discloses wherein the metal layer (8) comprises a first part (on 14) and a second part (on 9), the first part (on 14) is located in at least the main functional area (1), and the second part (on 9) is located in the transition area (3); and along a direction from the metal layer (8) to the semiconductor substrate (4), thickness of the first part (on 14) is greater than thickness of the second part (on 9) (See Fig. 1). As to claim 20, it would have been obvious Chen in view of Kaneda discloses wherein a thickness range of the first part (on 14) is [1 µm, 7 µm], and a thickness range of the second part (on 9) is [0.1 µm, 4 µm] as the thickness of the metal layer is about twice thick of the field oxide that is about 0.6 µm (See Kaneda Fig. 4, Fig. 5, Fig. 6, ¶ 0051). It would have been obvious to one of ordinary skill in the art to adjust the relative thicknesses in view of device properties and constraints such that a thicker metal layer may provide a lower resistance but a larger device size. Lastly, the applicant also has not established the critical nature of the “wherein a thickness range of the first part is [1 µm, 7 µm], and a thickness range of the second part is [0.1 µm, 4 µm]”, as the Specification merely discloses these values are examples. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims….In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to have various ranges. It would also have been obvious to one of ordinary skill in the art at the time the invention was made to discover the optimum or workable ranges by routine experimentations to adjust the dimensions such that optimized properties are obtained. See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Claim(s) 1 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2013/0105933 A1 to Sato (“Sato”) in view of U.S. Patent Application Publication No. 2017/0317068 A1 to Kaneda (“Kaneda”) and U.S. Patent Application Publication No. 2002/0190340 A1 to Moriguchi et al. (“Moriguchi”). As to claim 1, Sato in view of Kaneda and Moriguchi discloses a chip (Kaneda ¶ 0026 and Moriguchi 40), divided into a main functional area (20), a transition area (between 20 and 50 above 52), and a protection area (50), wherein the transition area (between 20 and 50 above 52) is located between the main functional area (20) and the protection area (50); the chip comprises a field oxide (58), a metal layer (22, 54), a main junction (52, 56), and a passivation layer (60) that are sequentially stacked on a semiconductor substrate (12), wherein the field oxide (58) and the passivation layer (60) are located in the transition area (between 20 and 50 above 52) and the protection area (50), and the metal layer (22, 54) is located in the main functional area (20) and the transition area (between 20 and 50 above 52); in the transition area (between 20 and 50 above 52), the field oxide (58) comprises a primary field oxide (58 right) and at least one secondary field oxide (58 left) that are disposed at intervals, wherein the secondary field oxide (58 left) is located on a side of the primary field oxide (58 right) facing the main functional area (20), the metal layer (22, 54) extends from the main functional area (20) to a side of the primary field oxide (58 right) facing away from the semiconductor substrate (12), and the passivation layer (60) extends from a side of the metal layer (22, 54) facing away from the semiconductor substrate (12) to a side of the metal layer (22, 54) facing away from the main functional area (20); and wherein the main junction (52, 56) extends from the main functional area (20) to the protection area (50) and is in contact with the at least one secondary field oxide (58 left), the primary field oxide (58 right) and at least a part of the field oxide (58) in the protection area (50) (See Fig. 1, ¶ 0022, ¶ 0023, ¶ 0025, ¶ 0026) (Notes: the protection area screens electrical influence on the interior). Although Sato does not specify the chip, the insulating layer (58) is the field oxide, and the emitter electrode (22) is the metal layer, Kaneda and Moriguchi disclose it is common the chip is divided into the main functional area, the transition area, and the protection area surrounding and protecting the main functional area and Kaneda further discloses the interlayer insulating film is commonly formed of the field oxide and the metal layer is commonly applied as a low resistance electrode (See Kaneda ¶ 0051, ¶ 0052). As to claim 21, Sato further discloses wherein along a direction away from the main functional area (20), a doping concentration of the main junction (52, 56) gradually decreases, and thickness of the main junction (52, 56) gradually decrease (See Fig. 1).
Response to Arguments
Applicant's arguments with respect to claims 1 and 13 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815