Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 12-19 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method of manufacturing a semiconductor device, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/18/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/20/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: the element number 295 appears in the drawings but is not mentioned in the specification.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Do (US 20220189944 A1) in view of Yun (US 11532695 B2).
Regarding claim 1, Do teaches, in FIGs. 1 and 9, a semiconductor structure comprising a “PFET region” (first FET) and a “NFET region” (second FET) AR2, a backside power delivery network comprising VDD and VSS lines (see FIG. 9) and “via patterns” (backside contacts) VA17 (first backside contact) and VA 13 (second backside contact).
Do does not teach a MIM capacitor plane beneath the first and second FET.
Yun teaches, in FIG. 11, a semiconductor structure, and states, in paragraph 10: “In various embodiments, MIM capacitors may be fabricated as part of a back-end-of-line (BEOL) process.” Yun further teaches, in FIG. 11, a MIM capacitor plane with a “bottom conductor plate layer” (first metal layer) 262) and a “middle conductor plate layer” (second metal layer) 266 with a “insulator layer” 264 formed therebetween. Additionally, “lower contact features” 254 and 255 are contacted by vias (first and second backside contacts) 287 and 289, respectively, wherein the backside contacts pass though the MIM capacitor plane and the first backside contact is electrically insulated from the first metal layer (“. . . as shown in the example of FIG. 11, the upper contact feature 287 . . . [is] electrically isolated from the top conductor plate layer 269. Further, the upper contact feature 289 . . . [is] electrically isolate[ed] from the middle conductor plate layer 266” (paragraph 42).
It would have been obvious to one having ordinary skill in the art to modify the semiconductor structure taught by Do such that the structure comprises a MIM capacitor plane beneath the first and second FETs (at the back-end of the device), as taught by Yun. One having ordinary skill in the art is motivated to do so because, for example, “in mixed-signal circuits, capacitors are used as decoupling capacitors and high-frequency noise filters” (Yun, paragraph 9).
Regarding claim 2, Do teaches that the first FET is a “PFET” and the second FET is an “NFET” (see above).
Regarding claim 3, Yun further teaches, in paragraph 25: “The middle conductor plate layer 266 may be formed in a way similar to that used to form the bottom conductor plate layer 262, but the pattern of the middle conductor plate layer 266 may be different from that of the bottom conductor plate layer 262. In an embodiment, the middle conductor plate layer 266 may include a metal nitride layer such as TiN, however other metals may be used.” The examiner notes that while TiN is also suggested for use in the first metal layer, Yun teaches that other metals can be used for the bottom layer, thereby teaching that the metal layers can be made of different metals.
It would have been obvious to one having ordinary skill in the art to modify the semiconductor structure taught by Do such that the first metal layer is a different type of metal than the second metal layer, as taught by Yun above. One having ordinary skill in the art would have a reasonable expectation of success when forming the first and second capacitor metal layers out of different metals, as all metals will perform the function of a capacitor electrode. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 4, Yun further teaches, in FIG. 11, a “barrier layer[s]” (dielectric spacers) 281 formed between the first backside contact 287 and the first metal layer and the second backside contact 289 and the second metal layer.
It would have been obvious to one having ordinary skill in the art to further modify the semiconductor structure taught by Do and Yun such that dielectric spacers are formed between the first and second backside contacts and the first and second metal layers, respectively. One having ordinary skill in the art is motivated to do so in order to, for example, ensure the electrical isolation of the first and second backside contacts and first and second metal layers, respectively.
Regarding claim 5, Do further teaches, in FIG. 1, that the first backside contact VA17 contacts the “source drain contact” CA17 in pFET region AR1 and the second backside contact VA13 contacts the “source/drain electrode” CA13 in the nFET region (AR2); also see FIG. 9.
Regarding claim 6, Do further teaches, in FIG. 9, a first backside power rail VDD which contacts the second backside contact and a second backside power rail VDD which contacts the first backside contact.
Regarding claim 7, Do further teaches, in 0047, that while the VDD power line contacts the first backside contact and the VSS power rail contacts the second backside contact, “For example, a positive (+) voltage may be applied to the first power supply wiring V.sub.DD, and . . . a negative (−) voltage may be applied to the second power supply wiring V.sub.SS, but the embodiment is not limited thereto.”
It would have been obvious to flip the VDD and VSS regions in the device taught by Do because it is the polarity between the source and drain across the depletion region that determines the operability of the device, VDD and VSS can be swapped as well as the source/drain connections in the source/drain regions of the nMOS and pMOS regions, creating a functionally identical device, as is well known to one having ordinary skill in the art.
Regarding claim 8, Yun further teaches, “the substrate 202 may also include an interconnect structure such as a multi-layer interconnect (MLI) structure . . . By way of example, the MLI structure, as well as other layers, features, components, or devices formed over the MLI structure may be formed as part of a BEOL process” (paragraph 15). Yun also teaches: “Although the lower contact features 253, 254, 255 are disposed below upper contact features (discussed below), the lower contact features 253, 254, 255 are sometimes referred to as top metal (TM) contacts because they represent a top metal layer of the MLI structure” (paragraph 22). The examiner notes that the MLI structure is homologous with a backside power delivery network. Yun further teaches, in FIG. 11, dielectric layers 256 and 258 between the MIM and the contacts 254 and 255 (insulation layers 256 and 258 form a backside interlayer dielectric layer between the MIM capacitor plane and the backside power delivery network).
It would have been obvious to one having ordinary skill in the art to further modify the device taught by Do such that there is a backside interlayer dielectric (ILD) layer between the MIM capacitor plane and the backside power delivery network. One having ordinary skill in the art is motivated to do so in order to, for example, ensure the electrical isolation of the backside power delivery network and the MIM capacitor.
Regarding claim 9, Do further teaches, in FIG. 1, that the first FET is laterally adjacent to the second FET.
Regarding claim 10, as explained above, the MIM capacitor plane taught by Yun further comprises a dielectric layer between the first metal layer and the second metal layer (see FIG. 9, insulating layer 264, further “to increase capacitance values, the insulator layer 268 may include high-k dielectric material(s)” as stated in paragraph 27).
It would have been obvious to further modify the device taught by Do such that the capacitor plane further comprises a dielectric layer between the first metal layer and the second metal layer. One having ordinary skill in the art is motivated to do so to increase capacitance values, as taught by Yun above.
Regarding claim 11, in FIG. 11, Yun further teaches a “dielectric portion” 271 between the MIM capacitor plane and above structures.
It would have been obvious to one having ordinary skill in the art to further modify the device taught by Do such that there is a dielectric layer between the MIM capacitor plane and the FETs there above. One having ordinary skill in the art is motivated to do so in order to, for example, ensure the electrical isolation of the FET and MIM structures.
Regarding claim 20, as shown above, Do teaches a semiconductor structure comprising a first and second source drain region, and first and second backside contacts and contacting the first and second source drain regions.
Do does not teach a MIM capacitor plane.
As stated above, Yun teaches a MIM capacitor plane in a back-end-of-line region (beneath upper regions) comprising and first and second metal layer, and first and second backside contacts passing through the MIM capacitor plane and contacting the first and second metal layers, respectively.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Do such that it comprises the MIM capacitor taught my Yun for the reasons stated above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jung (US 20220344463 A1) – Semiconductor structure with back end VDD and VSS power routing (see FIG. 10).
Chinthakini (US 20070057343 A1) – “Prior Art” figure 1C shows a MIM capacitor comprising a top and bottom electrode which are spaced apart via a MIM dielectric layer and sits above a BEOL layer with electrodes penetrating the capacitor plane.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights