Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 10, 16 – 18 are rejected under 35 U.S.C. 103 as being unpatentable over Uchiyama ( Pub. No. US 20210082877 A1 ), hereinafter Uchiyama, in view of Uchiyama.
PNG
media_image1.png
886
1430
media_image1.png
Greyscale
Regarding Independent Claim 1 ( Currently Amended ), Uchiyama teaches a semiconductor device comprising:
a plurality of transistors ( Uchiyama, FIG. 1, 31; [0027], transistors 31 );
a memory cell array ( Uchiyama, FIG. 1, 11; [0023], memory cell array 11 ) provided above the transistors ( Uchiyama, FIG. 1, 31; [0027] );
a first semiconductor layer ( Uchiyama, FIG. 1, SL, SL1, SL2; [0026], source line SL includes a first layer SL1, which is a semiconductor layer, and a second layer SL2, which is a metallic layer ) provided above the memory cell array and having a first surface located on a side on which the memory cell array is provided and a second surface opposite to the first surface;
a first metal wire ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026], source wiring layer 46; [0033], barrier metal layers … 46a, wiring material layers … 46b ) provided above the second surface and electrically connected to the first semiconductor layer ( Uchiyama, FIG. 1, SL; [0026] );
a second metal wire ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030], metal pad 45; [0033], barrier metal layers 45a, wiring material layers 45b ) provided above the second surface to be present in a same layer as the first metal wire and not to be in contact with the first metal wire ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) and the first semiconductor layer ( Uchiyama, FIG. 1, SL, SL1, SL2; [0026] );
a first contact ( Uchiyama, FIG. 1, 44b; [0029], via-plugs 44b ) provided below the first metal wire ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ), extending in a first direction from the first surface to the second surface, and configured to electrically connect one of the transistors ( Uchiyama, FIG. 1, 31; [0027] ) to the first metal wire ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ); and
a second contact ( Uchiyama, FIG. 1, 44a; [0029], via-plugs 44a ) provided below the second metal wire ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ), extending in the first direction, and configured to electrically connect another one of the transistors ( Uchiyama, FIG. 1, 31; [0027] ) to the second metal wire ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ),
Uchiyama does not explicitly disclose:
wherein in a plan view as viewed from the first direction, the first semiconductor layer and the second metal wire overlap.
However, Uchiyama teaches:
wherein in a plan view as viewed from the first direction, the first semiconductor layer ( Uchiyama, FIG. 1, SL, SL1, SL2 ) and the second metal wire ( Uchiyama, FIG. 1, 45, 45a, 45b );
FIG. 1, SL and 46 overlap; [0033], The metal pad 45 and the source wiring layer 46 in the present embodiment are provided in one and the same wiring layer … The metal pad 45 and the source wiring layer 46 in the present embodiment are formed by forming one wiring layer … Similarly, each of the lower surface of the metal pad 45 and the lower surface of the first portion R1 of the source wiring layer 46 is provided at a position higher than the upper surface of the source line SL; [0047], forms a wiring layer 48 on the source line SL and the insulating film 12 by sputtering; [0048], the metal pad 45 and the source wiring layer 46 are formed in the wiring layer 48; [0049], In this way, the metal pad 45 and the source wiring layer 46 in the present embodiment are formed by processing the same wiring layer 48.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Uchiyama ( SL and 46 overlap; the metal pad 45 ( i.e. barrier metal layers 45a and wiring material layers 45b ) and the source wiring layer 46 are provided in one and the same wiring layer 18; each of the lower surface of the metal pad 45 ( i.e. barrier metal layers 45a and wiring material layers 45b ) and the lower surface of the first portion R1 of the source wiring layer 46 is provided at a position higher than the upper surface of the source line SL ) to implement “SL and 45 / 45a / 45b overlap”, because the metal pad 45 ( i.e. barrier metal layers 45a and wiring material layers 45b ) and the source wiring layer 46 are provided in one and the same wiring layer 18. Doing so would fabricate SL and 45 / 45a / 45b at the same wiring layer, and therefore reduce the fabrication cost of multiple wiring layers.
Regarding Claim 2 ( Original ), Uchiyama teaches the device as claimed in Claim 1, Uchiyama further teaches:
comprising a first insulation layer ( Uchiyama, FIG. 1, 12; [0023], insulating film 12 ) provided on the first semiconductor layer ( Uchiyama, FIG. 1, SL, SL1, SL2; [0026] ), wherein a plurality of the second metal wires ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ) are provided on the first insulation layer ( Uchiyama, FIG. 1, 12; [0023] ) and electrically isolated from the first semiconductor layer ( Uchiyama, FIG. 1, SL, SL1, SL2; [0026] ) by the first insulation layer ( Uchiyama, FIG. 1, 12; [0023] ).
Regarding Claim 3 ( Original ), Uchiyama teaches the device as claimed in Claim 1, Uchiyama further teaches: further comprising a first insulation layer ( Uchiyama, FIG. 1, 12; [0023], insulating film 12 ) provided on the first semiconductor layer( Uchiyama, FIG. 1, SL, SL1, SL2; [0026] ), wherein
a plurality of the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) are provided on the first insulation layer ( Uchiyama, FIG. 1, 12; [0023] ) and electrically connected to the first semiconductor layer ( Uchiyama, FIG. 1, SL, SL1, SL2; [0026] ) via a plurality of third contacts ( Uchiyama, FIG. 1, R2; [0032], second portion R2 ) provided in the first insulation layer ( Uchiyama, FIG. 1, 12; [0023] ) ( Uchiyama, [0032], As a result, the source wiring layer 46 is provided on the source line SL in such a way as to be in contact with the source line SL and is electrically connected to the source line SL ).
Regarding Claim 4 ( Original ), Uchiyama teaches the device as claimed in Claim 1, Uchiyama further teaches:
wherein the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) and the second metal wires ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ) extend in a second direction ( Uchiyama, FIG. 1, x or y direction ) parallel to the second surface.
Regarding Claim 5 ( Original ), Uchiyama teaches the device as claimed in Claim 2, Uchiyama further teaches:
wherein the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) and the second metal wires ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ) extend in a second direction ( Uchiyama, FIG. 1, x or y direction ) parallel to the second surface.
Regarding Claim 6 ( Original ), Uchiyama teaches the device as claimed in Claim 3, Uchiyama further teaches:
wherein the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) and the second metal wires ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ) extend in a second direction ( Uchiyama, FIG. 1, x or y direction ) parallel to the second surface.
Regarding Claim 7 ( Currently Amended ), Uchiyama teaches the device as claimed in Claim 4, Uchiyama further teaches:
wherein, in the plan view as viewed from the first direction ( Uchiyama, FIG. 1, z direction ),
the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) and the second metal wires ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ) are alternately arranged in a third direction (Uchiyama, FIG. 1, x direction) that crosses the first and second directions ( Uchiyama, FIG. 1, z direction and y direction ) at substantially right angles.
Regarding Claim 8 ( Original ), Uchiyama teaches the device as claimed in Claim 7, Uchiyama further teaches: further comprising a first electrode ( Uchiyama, FIG. 1, 45a; [0033], barrier metal layers 45a ) provided above the second surface and electrically isolated ( Uchiyama, FIG. 1, 12; [0023], insulating film 12 ) from the first semiconductor layer ( Uchiyama, FIG. 1, SL, SL1, SL2), wherein
the second metal wires ( Uchiyama, FIG. 1, 45b; [0033], wiring material layers 45b ) are electrically connected to the first electrode ( Uchiyama, FIG. 1, 45a; [0033] ).
Regarding Claim 9 ( Original ), Uchiyama teaches the device as claimed in Claim 8, Uchiyama further teaches: further comprising a fourth contact ( Uchiyama, FIG. 1, 44a; [0029], via-plugs 44a ) provided to extend in the first direction ( Uchiyama, FIG. 1, z direction ) and connected (Uchiyama, FIG. 1, 35; [0027], wiring layers 35) between the first electrode ( Uchiyama, FIG. 1, 45a; [0033] ) and a third one of the transistors ( Uchiyama, FIG. 1, 31; transistor 31 ).
Regarding Claim 10 ( Currently Amended ) , Uchiyama teaches the device as claimed in Claim 9, Uchiyama further teaches:
wherein, in the plan view as viewed from the first direction,
the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) each have a rectangular shape with its longitudinal direction along the second direction ( Uchiyama, FIG. 1, x or y direction ), and
each of the second metal wires ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ) extends between the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) and electrically connects the second contact and the fourth contact ( Uchiyama, FIG. 1, 44a; [0029], via-plugs 44a ) to each other.
Regarding Claim 16 ( Currently Amended ), Uchiyama teaches the device as claimed in Claim 1, Uchiyama further teaches: further comprising a wire ( Uchiyama, FIG. 1, CL; [0026], columnar portion CL ) penetrating through the memory cell array ( Uchiyama, FIG. 1, 11; [0028] ) to be connected to the first semiconductor layer ( Uchiyama, FIG. 1, SL, SL1, SL2; [0026] ) while being electrically isolated from the memory cell array, wherein
the wire ( Uchiyama, [0026], Each columnar portion CL, which penetrates through a plurality of word lines WL, is electrically connected to a bit line BL via a via-plug 24, and is also electrically connected to the source lune SL ) extends in a direction crossing the first ( Uchiyama, FIG. 1, 46, 46a, 46b, [0026] ) and second ( Uchiyama, FIG. 1, 45, 45a, 45b ) metal wires in the plan view as viewed from the first direction.
Regarding Claim 17 ( Currently Amended ), Uchiyama teaches the device as claimed in Claim 16, Uchiyama further teaches:
wherein the wire crosses the first ( Uchiyama, FIG. 1, 46, 46a, 46b, [0026] ) and second ( Uchiyama, FIG. 1, 45, 45a, 45b ) metal wires at substantially right angles in the plan view as viewed from the first direction ( Uchiyama, [0026], Each columnar portion CL, which penetrates through a plurality of word lines WL, is electrically connected to a bit line BL via a via-plug 24, and is also electrically connected to the source lune SL ).
Regarding Claim 18 ( Original ), Uchiyama teaches the device as claimed in Claim 16, Uchiyama further teaches:
wherein the wire includes an insulating film provided on an inner wall of a slit that penetrate through the memory cell array and reaches the first semiconductor layer, and a conductive material embedded inside the insulating film ( Uchiyama, [0038], The columnar portion CL includes, in order, a block insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56 ).
Claims 11 – 13 are rejected under 35 U.S.C. 103 as being unpatentable over Uchiyama, in view of Lindsay (Pub. No. 20050090085 A1), hereinafter Lindsay.
Regarding Claim 11 ( Currently Amended ), Uchiyama teaches the device as claimed in Claim 10, Uchiyama further teaches: wherein, in the plan view as viewed from the first direction,
sides of the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ), facing the second metal wires ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ), are with respect to the second direction, and
sides of the second metal wires ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ), facing the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ), are with respect to the second direction.
Uchiyama fails to disclose:
sides of the first metal wires, facing the second metal wires, are inclined with respect to the second direction, and
sides of the second metal wires, facing the first metal wires, are inclined with respect to the second direction.
However, Lindsay teaches:
sides of the first metal wires, facing the second metal wires, are inclined ( Lindsay, FIG. 3, the width of drain contacts 330 is varied or inclined with respect to the horizontal direction ) with respect to the second direction, and
sides of the second metal wires, facing the first metal wires, are inclined ( Lindsay, FIG. 3, the width of drain contacts 330 is varied or inclined with respect to the horizontal direction ) with respect to the second direction.
Uchiyama and Lindsay are both considered to be analogous to the claimed invention because they are forming NAND memory device. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Uchiyama ( first metal wires 46 and second metal wires 45 ), to incorporate the teachings of Lindsay ( the width of drain contacts 330 is varied or inclined ), to implement that “ sides of the first metal wires, facing the second metal wires, are inclined ”. Doing so would provide specific layout for the shape of first metal wires and second metal wires, and resistance of contacts and paths are reduced, and the performance of NAND memory device is improved.
Regarding Claim 12 ( Currently Amended ), Uchiyama and Lindsay teach the device as claimed in Claim 10, Uchiyama and Lindsay further teach: wherein, in the plan view as viewed from the first direction,
a width of each of the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) in a third direction crossing the first and second directions at substantially right angles becomes larger ( Lindsay, FIG. 3, for the drain contacts 330 on the top, the width becomes larger from left to right with respect to the horizontal direction ) with increase in a distance from the first contact in the second direction.
Regarding Claim 13 ( Currently Amended ), Uchiyama and Lindsay teach the device as claimed in Claim 11, Uchiyama and Lindsay further teach: wherein, in the plan view as viewed from the first direction,
a width of each of the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) in a third direction crossing the first and second directions at substantially right angles becomes larger ( Lindsay, FIG. 3, for the drain contacts 330 on the top, the width becomes larger from left to right with respect to the horizontal direction ) with increase in a distance from the first contact in the second direction.
Claims 14 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Uchiyama, in view of Lee (Pub. No. 20130009236 A1), hereinafter Lee.
Regarding Claim 14 ( Currently Amended ), Uchiyama teaches the device as claimed in Claim 10, Uchiyama further teaches: wherein, in the plan view as viewed from the first direction,
a width of each of the first metal wires ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ), and
a width of each of the second metal wires ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ).
Uchiyama fails to disclose:
a width of each of the first metal wires in a third direction crossing the first and second directions at substantially right angles is larger at a center in the second direction of the first metal wire than at each end in the second direction of the first metal wire, and
a width of each of the second metal wires in the third direction is smaller at a center in the second direction of the second metal wire than at each end in the second direction of the second metal wire.
However, Lee teaches:
a width of each of the first metal wires in a third direction crossing the first and second directions at substantially right angles is larger at a center ( Lee, gate stacks 303, in which the width is larger at the center, than the width at each end ) in the second direction of the first metal wire than at each end in the second direction of the first metal wire, and
a width of each of the second metal wires in the third direction is smaller at a center ( Lee, strapping lines 393, in which the width is smaller at the center, than the width at each end ) in the second direction of the second metal wire than at each end in the second direction of the second metal wire.
Uchiyama and Lee are both considered to be analogous to the claimed invention because they are forming memory device. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Uchiyama ( first metal wires 46 and second metal wires 45 ), to incorporate the teachings of Lindsay ( the width of gate stacks 303 is larger at the center, the width of strapping lines 393 is smaller at the center ), to implement that “ a width of each of the first metal wires is larger at a center, a width of each of the second metal wires is smaller at a center ”. Doing so would provide specific layout for the shape of first metal wires and second metal wires, and resistance of contacts and paths are reduced, and the performance of memory device is improved.
Regarding Claim 15 ( Currently Amended ), Uchiyama and Lee teach the device as claimed in Claim 11, Uchiyama and Lee further teach: wherein, in the plan view as viewed from the first direction,
a width of each of the first metal ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) wires in a third direction crossing the first and second directions at substantially right angles is larger at a center ( Lee, gate stacks 303, in which the width is larger at the center, than the width at each end ) in the second direction of the first metal wire ( Uchiyama, FIG. 1, 46, 46a, 46b; [0026] ) than at each end in the second direction of the first metal wire, and
a width of each of the second metal wires ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ) in the third direction is smaller at a center ( Lee, strapping lines 393, in which the width is smaller at the center, than the width at each end ) in the second direction of the second metal wire ( Uchiyama, FIG. 1, 45, 45a, 45b; [0030] ) than at each end in the second direction of the second metal wire.
Response to Arguments
Applicant's remarks filed 11/13/2025 have been fully considered but they are not persuasive.
Applicant’s remarks regarding ( Currently Amended ) Claims 1: on page 8, line 4, cited “ Applicant respectfully submits that the art fails to disclose or suggest the claimed features. For example, Uchiyama is silent at least with respect to, in a plan view as viewed from the first direction (in a non-limiting example, Z), the first semiconductor layer (in a non- limiting example, BSL) and the second metal wire (in a non-limiting example, 41 (ps. this should be 42)) overlap. The outstanding Office Action asserts that Uchiyama's element SL corresponds to the "first semiconductor layer" of Claim 1, and Uchiyama's element 45 corresponds to the "second metal wire" of Claim 1. However, taking this assertion into account, Uchiyama's source line (element SL) does not overlap with metal pad (element 45) in a plan view from the Z direction (see Figure 1 of Uchiyama). ”.
Examiner’s response: please refer to claims 1 in Claim Rejections - 35 USC § 103 of this office action, cited “Uchiyama does not explicitly disclose:
wherein in a plan view as viewed from the first direction, the first semiconductor layer and the second metal wire overlap.
However, Uchiyama teaches:
wherein in a plan view as viewed from the first direction, the first semiconductor layer ( Uchiyama, FIG. 1, SL, SL1, SL2 ) and the second metal wire ( Uchiyama, FIG. 1, 45, 45a, 45b );
FIG. 1, SL and 46 overlap; [0033], The metal pad 45 and the source wiring layer 46 in the present embodiment are provided in one and the same wiring layer … The metal pad 45 and the source wiring layer 46 in the present embodiment are formed by forming one wiring layer … Similarly, each of the lower surface of the metal pad 45 and the lower surface of the first portion R1 of the source wiring layer 46 is provided at a position higher than the upper surface of the source line SL; [0047], forms a wiring layer 48 on the source line SL and the insulating film 12 by sputtering; [0048], the metal pad 45 and the source wiring layer 46 are formed in the wiring layer 48; [0049], In this way, the metal pad 45 and the source wiring layer 46 in the present embodiment are formed by processing the same wiring layer 48.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Uchiyama ( SL and 46 overlap; the metal pad 45 ( i.e. barrier metal layers 45a and wiring material layers 45b ) and the source wiring layer 46 are provided in one and the same wiring layer 18; each of the lower surface of the metal pad 45 ( i.e. barrier metal layers 45a and wiring material layers 45b ) and the lower surface of the first portion R1 of the source wiring layer 46 is provided at a position higher than the upper surface of the source line SL ) to implement “SL and 45 / 45a / 45b overlap”, because the metal pad 45 ( i.e. barrier metal layers 45a and wiring material layers 45b ) and the source wiring layer 46 are provided in one and the same wiring layer 18. Doing so would fabricate SL and 45 / 45a / 45b at the same wiring layer, and therefore reduce the fabrication cost of multiple wiring layers. ”. Based on above reasons, “SL and 45a / 45b overlap” is obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached Monday thru Friday E.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit:
https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817