DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/04/2025 has been considered by the examiner.
Response to Amendment
The indicated allowability of claims 1 and 11-19 are withdrawn in view of the newly discovered reference(s) to Myoung (KR 101781799) as submitted by the Applicant filed on 12/04/2025, Youn (US 2011/037158) and Hwang (US 2020/0135699). Rejections based on the newly cited reference(s) follow:
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Myoung (KR 10-1781799; hereinafter Myoung) as submitted by the Applicant filed on 12/04/2025.
Regarding claim 1, Myoung teaches a stack package in fig. 6 comprising:
a first die stack (200) including first dies;
a second die stack (220) including second dies; and
an insert die (refer to one of die in the middle stack 210) between the first die stack (200) and the second die stack (220), the insert die being thicker than each of the first and second dies (see fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is are rejected under 35 U.S.C. 103 as being unpatentable over Myoung (KR 10-1781799) as applied to claim 1 above.
Regarding claim 2, Myoung teaches all the limitations of the claimed invention for the same reasons as set forth above except for a top die that is bonded to the second die stack, the top die being thicker than each of the second dies.
Fig. 4 of Myoung teaches another embodiment wherein a top die (30) that is bonded to the second die stack (refer to upper stacked dies 20), the top die being thicker than each of the second dies (see fig.4).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a top die that is bonded to the second die stack, the top die being thicker than each of the second dies as shown in another embodiment to fig. 5 Myoung in order to prevent the chips from bending downwardly of the substrate by molding pressure.
Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Myoung as applied to claim 1 above, and further in view of Youn (US 20110037158).
Regarding claim 3, Myoung teaches all the limitations of the claimed invention for the same reasons as set forth above except for the first dies comprise first through vias, and the insert die comprises second through vias that electrically connect the first through v as to the second dies.
Youn teaches the same field of an endeavor wherein the first dies (refer to bottom most stacked dies CG1 and CG2) comprise first through vias (145e/145f), and the insert die (refer to middle die CG1/CG2) comprises second through vias (refer to 145e/145f that extend through the middle die CG1/CG2) that electrically connect the first through vias (refer to 145e/145f that extending through the bottom most CG1and CG2) to the second dies (refer to the upper most CG1 and CG2 in fig. 8 and par. 86).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the first dies comprise first through vias, and the insert die comprises second through vias that electrically connect the first through v as to the second dies as taught by Youn in the teaching of Myoung in order to reducing spaces between adjacent chips by using through vias connections from the top chip to the bottom chip (see par. 91).
Regarding claim 4, Myoung and Youn teach all the limitations of the claimed invention for the same reasons as set forth above. Combining the TSV of Youn in the stacked dies structure of Myong because the middle die of Myong is thicker than the lower die so that the each of the second through vias is longer than each of the first through vias (see fig. 8 of Youn and fig. 6 of Myong).
Regarding claim 5, Myoung teaches all the limitations of the claimed invention for the same reasons as set forth above except for the insert die comprises first and second bonding surfaces that are opposite to each other, the first bonding surface of the insert die is directly bonded to a third bonding surface of the first die that is disposed at a highest layer of the first dies, and the second bonding surface of the insert die is directly bonded to a fourth bonding surface of the second die that is disposed at a lowest layer of the second dies.
Fig. 8 of Youn teaches the same field of an endeavor wherein the insert die (refer to middle die CG1/CG2) comprises first and second bonding surfaces (refer to lower and upper surfaces of the middle die CG1/CG2) that are opposite to each other, the first bonding surface of the insert die (refer to lower surface of the middle die CG1/CG2) is directly bonded to a third bonding surface of the first die (refer to upper surface of the bottom most dies CG2) that is disposed at a highest layer of the first dies, and the second bonding surface of the insert die (refer to the upper surface of CG1/CG2) is directly bonded to a fourth bonding surface of the second die (refer to lower surface of the bottom stacked die CG1/CG2) that is disposed at a lowest layer of the second dies.
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the insert die comprises first and second bonding surfaces that are opposite to each other, the first bonding surface of the insert die is directly bonded to a third bonding surface of the first die that is disposed at a highest layer of the first dies, and the second bonding surface of the insert die is directly bonded to a fourth bonding surface of the second die that is disposed at a lowest layer of the second dies as taught by Youn in the teaching of Myoung in order to reduce the thickness between adjacent chips by using directly bonding method (see par. 84).
Regarding claim 6, Myoung and Youn teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Youn teaches a first dummy metal layer (refer to dummy chip pad 135e/135f; see par. 86) under the third bonding surface of the first die (refer to upper surface CG2 of the bottom stacked dies CG2/CG1) that is disposed at the highest layer of the first dies (see fig. 8).
Regarding claim 7, Myoung and Youn teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Youn teaches a second dummy metal layer (refer to dummy chip pad 135e/135f see par. 86) over the fourth bonding surface of the second die that is disposed at the lowest layer of the second dies (refer to lower surface of the lower chip CG1 in the upper stacked dies CG1/CG2).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Myoung as applied to claim 1 above, and further in view of Hwang (US 20200135699).
Regarding claim 8, Myoung teaches all the limitations of the claimed invention for the same reasons as set forth above except for bonding surfaces of the first dies that face each other are directly bonded together.
Fig. 1 of Hwang teaches bonding surfaces of the first dies (refer to 164 and 162 of 100A-100B) that face each other are directly bonded together.
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include bonding surfaces of the first dies that face each other are directly bonded together as taught by Hwang in the teaching of Myoung in order to provide relatively high electrical reliability (reduction in transmission loss) and relatively high structural reliability may be implemented, as well as the miniaturization (slimming) of the semiconductor package (see par. 41).
Regarding claim 9, Myong teaches all the limitations of the claimed invention for the same reasons as set forth above except for bonding surfaces of the second dies that face each other are directly bonded together.
Fig. 1 of Hwang teaches bonding surfaces of the second dies (refer to 164 and 162 of chips 100C-100B) that face each other are directly bonded together.
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include bonding surfaces of the second dies that face each other are directly bonded together as taught by Hwang in the teaching of Myong in order to provide relatively high electrical reliability (reduction in transmission loss) and relatively high structural reliability may be implemented, as well as the miniaturization (slimming) of the semiconductor package (see par. 41).
Claims 10,12, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Youn (US 2011/0037158), and further in view of Hwang (US 20200135699).
Regarding claim 10, Youn teaches a stack package in fig.8 comprising:
a first die stack including first dies (refer to bottom stacked chip CG1/CG2);
a second die stack including second dies (refer to upper stacked CG1/CG2);
an insert die (refer to middle die CG1/CG2) inserted between the first die stack and the second die stack (refer to bottom stacked dies CG1/CG2 and upper stacked dies CG1/CG2), the insert die including first and second bonding surfaces that are opposite to each other (refer to a lower surface and an upper surface of the middle die CG1/CG2); and
a third dummy metal layer (refer to dummy chip pad 135e/135f in par. 86) disposed over the first bonding surface (refer to the lower surface of the middle die CG1/CG2) or under the second bonding surface of the insert die (refer to the upper surface of the middle die CG1/CG2).
Youn does not teach wherein bonding surfaces of the first dies that face each other are directly bonded together.
Fig. 1 of Hwang teaches a same field of an endeavor wherein bonding surfaces of the stacked dies (refer to 164 and 162 of chips 100A-100B) that face each other are directly bonded together.
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include bonding surfaces of the first dies that face each other are directly bonded together as taught by Hwang in the teaching of Youn in order to provide relatively high electrical reliability (reduction in transmission loss) and relatively high structural reliability may be implemented, as well as the miniaturization (slimming) of the semiconductor package (see par. 41).
Regarding claim 12, Youn and Hwang teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 1 of Hwang shows the first bonding surface of the insert die (refer to lower surface 162 of chip 100C) is directly bonded to a third bonding surface of the first die (refer to upper surface 164 of 100B) that is disposed at a highest layer of the first dies; and the second bonding surface of the insert die (refer to upper surface 164 of middle chip 100C) is directly bonded to a fourth bonding surface of the second die (refer to lower surface 162 of chip 100D) that is disposed at a lowest layer of the second dies (see fig. 1).
Regarding claim 16, Youn and Hwang teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 8 of Youn shows the first dies (refer to bottom stacked dies CG1/CG2) comprise first through vias (refer to 145e/145f that extending through the bottom stacked dies CG1/CG2), and the insert die (refer to middle die CG1/CG2) further comprises second through vias (refer to 145e/145f that extending through the middle die CG1/CG2) that electrically connect the first through vias (refer to 145e/145f that extending through the bottom stacked dies CG1/CG2) to the second dies (refer to upper stacked dies CG1/CG2).
Regarding claim 19, Youn and Hwang teach all the limitations of the claimed invention for the same reasons as set forth above. Fig. 1 of Hwang teaches bonding surfaces of the second dies (refer to 164 and 162 of 100D-100C) that face each other are directly bonded together.
Claims 11,15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Youn (US 2011/0037158) in view of Hwang (US 2020/0135699), and further in view of Myoung (KR 10-1781799).
Regarding claim 11, Youn and Hwang teach all the limitations of the claimed invention for the same reasons as set forth above except for the insert die is thicker than each of the first and second dies.
Fig. 6 of Myoung teaches the same field of an endeavor wherein the insert die (refer to one of die 210) is thicker than each of the first and second dies (refer to stacked dies 200 and 220).
Thus, it would be obvious to one having ordinary skills in the art before the invention was made to include the insert die is thicker than each of the first and second dies as taught by Myoung in the teaching of Youn and Hwang in order to prevent the chip warping phenomenon.
Regarding claim 15, Youn and Hwang teach all the limitations of the claimed invention for the same reasons as set forth above except for shows a top die that is bonded to the second die stack, the top die being thicker than each of the second dies.
Fig. 4 of Myong teaches a same field of an endeavor wherein a top die (30) that is bonded to the second die stack (refer to upper stacked dies 20), the top die being thicker than each of the second dies (see fig.4).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a top die that is bonded to the second die stack, the top die being thicker than each of the second dies as taught by Myoung in the teaching of Young and Hwang in order to prevent the chips from bending downwardly of the substrate by molding pressure.
Regarding claim 17, Youn and Hwang teach all the limitations of the claimed invention for the same reasons as set forth above except for each of the second through vias is longer than each of the first through vias.
Fig. 6 of Myoung teaches the same field of an endeavor wherein a middle die (210) is thicker than the lower stacked dies (200).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the middle die is thicker than the lower stacked dies as taught by Myoung in the teaching of Youn and Hwang so that it prevent the chip warpage phenomenon.
Replacing the middle die of Myoung (210) to the middle die of Youn (refer to middle die CG1/CG2) in stacked package as shown in fig. 8 of Youn. Thus, it would be obvious to have the through vias of the middle dies is longer than each of the first trhough vias.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818