DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/24/26 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukuyama et al, JP patent 2004-099394, in view of Chan et al, US Pub. 2021/0239647, and further in view of Chen, CN 104766903.
Regarding claim 1, Fukuyama et al teach a method for manufacturing a microlens-array structure and explain that microlens arrays comprise fine lenses arranged on a substrate and are useful in optical communications ( ¶¶ [0001]-[0003]) comprising: depositing a first mask over a support material ( ¶ [0026] depositing silicon thin film 2 over glassy-carbon substrate 1. The silicon thin film subsequently functions as etching mask 2a); wherein the depositing the first mask comprises using chemical vapor deposition, atomic layer deposition, physical vapor deposition, or an oxidation process ( ¶ [0026] that silicon thin film 2 may be deposited over substrate 1 using plasma CVD); thus expressly teaches one of the alternative deposition processes recited); further teach at ¶¶ [0027]-[0028] patterning photoresist 3 and anisotropically etching silicon thin film 2 to transfer the pattern into the silicon thin film, thereby producing patterned silicon thin-film etching mask 2a; forming a concave surface in the support material through the first mask ( ¶ [0029] isotropically etching glassy-carbon substrate 1 using silicon thin-film pattern 2a as the etching mask. The etching proceeds isotropically from the bottoms of the mask openings into substrate 1, thereby forming concave lens-shaped depressions in the surface of substrate 1. See also Fig. 1(d)-(e). Thus, teach the claimed sequence of: CVD deposition of first mask → patterning first mask → etching underlying support material through first mask → formation of concave surface.
Fukuyama et al fail to teach bonding the first mask to a first bonding layer over an optical interposer.
Chang et al teach the relationship between a deposited hard mask, a bonding area, subsequent substrate etching, and a bonding layer; wafer-level fabrication in which a hard mask is deposited specifically over regions of a substrate that are intended to serve as bonding areas. In the fabrication sequence associated with the cap structure, Chang teaches that the bonding areas of cap structure substrate 230 correspond to bonding sites on buried oxide layer 206. Chang expressly states that the bonding areas interface with the bonding sites when the cap structure is subsequently bonded to the buried oxide layer or to an intermediate bonding layer deposited and patterned on the buried oxide layer. Chang et al then teach depositing a hard mask on the bonding areas of the cap structure substrate; the hard mask protects the bonding areas during subsequent etching. Chang expressly teaches that the hard mask may comprise oxide and may be formed by CVD. See the description corresponding to the cap-structure fabrication process and Figs. 12-15, particularly the teachings associated with deposition of hard mask 236. Chang et al further teach that after the hard mask is deposited, cap structure substrate 230 is etched to form channels. The bonding areas remain covered by hard mask 236. During the subsequent blanket etch used to form chamber 244, the bonding areas covered by hard mask 236 are protected from etching. Accordingly, Chang et al establish that it was known to: deposit a hard mask over a substrate bonding area to retain that hard mask during subsequent substrate etching → use the protected area as the interface for subsequent bonding to another layer/structure. Chang et al additionally teaches that substrates may be attached using fusion, diffusion, eutectic, and/or other suitable bonding methods. Therefore, it would have been obvious for an ordinary artisan to modify the Fukuyama’s process such that the mask is retained over a region intended for subsequent bonding instead of being removed immediately after the substrate etching operation.
Fukuyama et al as modified by Chang et al fail to expressly disclose an optical interposer as presently claimed.
Chen discloses an optical interposer; Chen is directed to integrated optoelectronic packaging and expressly defines an optoelectronic IC as a chip containing at least one optical element, including a photodetector, laser, optical modulator, waveguide, or optical coupler; expressly teaches in connection with Fig. 3 an optical/optoelectronic packaging architecture employing interposer 400 having through-silicon vias (TSVs) 440; teaches that optoelectronic IC 200 containing optical element 202 is mounted on interposer 400, and electronic IC 300 is also mounted on interposer 400. Electrical contacts of the optoelectronic IC and electronic IC communicate through the interposer. See the description associated with Fig. 3; further explains that light enters the optoelectronic IC and travels to photodetector 202, with the resulting electrical signal transmitted to electronic IC 300 through the electrical path of interposer 400. Thus, Chen establishes that optical devices and electronic ICs were conventionally integrated using an interposer architecture.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fukuyama et al as modified by Chang et al such that an appropriate hard-mask material is retained at the intended bonding region following formation of the concave optical surface, rather than necessarily removing the entire mask as described in Fukuyama. Therefore, it would have been an obvious extension as taught by the prior art.
Regarding claim 2, in addition to the rejection of claim 1 above; Chang et al further teach that its deposited hard mask may comprise an oxide hard mask. The use of silicon oxide as the dielectric hard-mask/bonding-interface material would have been an obvious selection because oxide hard masks were known for protecting silicon/substrate surfaces during etching and for providing dielectric surfaces compatible with wafer bonding. Therefore, it would have been obvious over Fukuyama in view of Chang and Chen.
Regarding claim 3, in addition to the rejection of claim 1 above, Chang et al further teach wafer/substrate bonding and identifies fusion bonding among suitable bonding techniques. It therefore would have been obvious to employ fusion bonding to bond the protected dielectric bonding interface to the corresponding bonding layer because fusion bonding was a known wafer-level bonding technique providing direct bonding between compatible dielectric surfaces. Therefore, it would have been obvious over Fukuyama in view of Chang et al and Chen.
Regarding claim 4, Chen expressly teaches integration of an electronic IC 300 with an optoelectronic IC and an interposer. Fig. 3 and associated description, teaches optoelectronic IC 200 and electronic IC 300 mounted in an interposer-based architecture. Chen further teaches other vertically integrated configurations in which the electronic IC is positioned in the optical/electronic package stack. It would have been obvious to position the electronic integrated circuit between the bonding/interface structure and optical interposer as a known stacked arrangement for compact heterogeneous optical/electronic integration. Therefore, it would have an obvious extension as taught by the prior art.
Claim 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Chang et al and further in view of Fukuyama et al.
Regarding claim 8, Chen teaches integrated optical/electronic packaging employing electronic IC 300, optoelectronic IC 200, and interposer 400 (Fig. 3 and associated description). Chen expressly teaches that optoelectronic IC 200 having optical element 202 is mounted on interposer 400 and that electronic IC 300 is likewise mounted on interposer 400. The components communicate electrically through TSVs 440 of the interposer.
Chen fails to disclose depositing/providing bonding-interface material in wafer-level packaging and subsequent bonding of substrate structures to corresponding bonding areas, including intermediate bonding-layer arrangements.
Chang et al teaches depositing/providing bonding-interface material in wafer-level packaging and subsequent bonding of substrate structures to corresponding bonding areas, including intermediate bonding-layer arrangements.
It would have been obvious to use the wafer-level bonding technique taught by Chang et al in order to provide compact optical coupling, which therefore obvious.
Chen as modified by Chang et al to disclose that the manufacture of the required concave surface substrate, including substrate and deposited silicon thin-film mask, with concave lens-shaped depressions formed in substrate through the mask
Fukuyama teaches the manufacture of the required concave surface substrate, including substrate 1 and deposited silicon thin-film mask 2a, with concave lens-shaped depressions formed in substrate 1 through the mask (¶¶ [0026]–[0029]).
It would have been obvious to integrate Fukuyama’s known concave optical substrate into the stacked optical/electronic package of Chen using the wafer-level bonding techniques taught by Chang et al to provide compact optical coupling in an integrated optical/electronic package. The combination would further have resulted in a mask material different from the support material because Fukuyama et al employs a silicon thin-film mask over a glassy-carbon support substrate. Therefore, it would have been obvious extension as taught by the prior art.
Regarding claim 9, Chang et al further teach use of oxide hard-mask material. Selection of silicon oxide as the mask/bonding dielectric would have been an obvious implementation of a dielectric hard mask suitable for wafer-level bonding. Therefore, claim 9 would have been obvious.
Claims 15-20 is rejected under 35 U.S.C. 103 as being unpatentable over Fukuyama et al in view of Chang et al and further in view of CN104766903A.
Fukuyama et al teach a concave surface substrate comprising: support substrate 1; silicon thin-film mask material 2a different from the support material; and a concave lens-shaped surface formed within the support material. See Fukuyama ¶¶ [0026]–[0029] and Fig. 1.
Chang et al teach wafer-level structures having a bonding interface/bonding layer associated with a substrate bonding region.
Chen teaches an electronic IC integrated with an optical/optoelectronic device and interposer. In particular, Fig. 3 teaches electronic IC 300 and optoelectronic IC 200 associated with interposer 400.
It would have been obvious to integrate Fukuyama et al’s known concave optical substrate into the bonded optoelectronic/interposer structure taught by Chen using Chang’s wafer-level bonding teachings to provide a compact optical/electronic integrated package. The resulting structure would comprise a concave substrate having a distinct mask material, a bonding layer associated with that mask/interface, an electrical integrated circuit adjacent the bonding layer, and an optical interposer associated with/bonded to the electrical integrated circuit. Therefore, claim 15 would have been obvious.
Regarding claim 16, Chang et al teach use of an oxide hard mask at a bonding region. Use of silicon oxide for such dielectric hard masks and wafer-level dielectric bonding interfaces was known and would have been an obvious material selection. Accordingly, claim 16 would have been obvious.
Regarding claim 17, additionally requires the support material to comprise silicon.
The use of silicon as the substrate/support material in semiconductor and silicon-photonics structures was conventional, and Chang et al’s wafer-level fabrication is based on semiconductor substrates. Selection of silicon for the support substrate would have been predictable where the resulting optical structure is incorporated into a silicon-based optical/electronic package. Accordingly, claim 17 would have been obvious.
Allowable Subject Matter
Claims 5-7, 10-14, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The applicant teaches an optical device and a method of manufacturing the optical device which includes a concave surface having a support material, a first mask, a concave surface formed within the support material, a bonding layer bonded to the first mask material, forming a second side of the concave surface substrate opposite the first side, an optical interposer bonded to the electrical integrated circuit, wherein the concave surface substrate further includes an anti-reflective layer adjacent to the concave surface and a fill material adjacent to the anti-reflective layer and planar with the first mask material. These limitations in conjunction with other limitations in the claims were not shown by the prior art of record.
Response to Arguments
Applicant's arguments filed 7/24/26 have been fully considered but they are not persuasive. See examiner remarks.
Remarks:
In response to the applicant’s argument that the prior art (Chen, CN 104766903) fails to disclose forming a concave surface in the support material through the first mask and bonding the first mask to a bonding layer over an optical interposer, the examiner respectfully disagrees. the prior art teaches forming a method of integrated module, comprising: a first semiconductor substrate forms a surface projection structure and a first power pad; a second semiconductor substrate forms a concave surface structure and a second electrical pad, the first semiconductor substrate to the second semiconductor substrate and the bump on the surface structure is substantially matched with the hollowed structure on aluminum sheet surface, and is electrically connected to the first pad and the second pad are aligned, the applying comprises heating. pressing or a combination of chemical or physical force to engage the first semiconductor substrate and the second semiconductor substrate (see claim 18 and summary of the invention). The prior art teaches using silicon via TSV interposer (440) with a light element 202, at least mask 200/300, and a bonding layer 130 (see Fig. 3). With respect to the amendments, the new prior arts (Chang et al and Fukuyama et al) meets claims’ language. The applicant’s arguments are not persuasive. Refer to the rejection above.
Conclusion
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DANIEL ST CYR
Primary Examiner
Art Unit 2876
/DANIEL ST CYR/ Primary Examiner, Art Unit 2876
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