Prosecution Insights
Last updated: July 17, 2026
Application No. 18/186,413

Optical Device and Method of Manufacture

Non-Final OA §102
Filed
Mar 20, 2023
Examiner
ST CYR, DANIEL
Art Unit
2876
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Non-Final)
81%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
1147 granted / 1409 resolved
+13.4% vs TC avg
Moderate +13% lift
Without
With
+13.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
39 currently pending
Career history
1439
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
47.8%
+7.8% vs TC avg
§102
14.2%
-25.8% vs TC avg
§112
1.5%
-38.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1409 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen, CN 104766903. Chen discloses an integrated mode and its forming method comprising: an integrated module, the integration module comprises a first unit (e.g. an electronic IC 300) and a second unit (e.g. a photoelectric IC (200), wherein the light emitted by the photoelectric element back surface, and the back surface is the light element 202 the position of the opposite surface. In order to achieve effective coupling, photoelectric IC comprising a OTSV (for example, FIG. 12A-12D, FIG. 13A-13E or other drawn OTSV). to direct light into a photoelectric IC is capable of polishing or grinding to thin thickness. According to some embodiments, photoelectric IC can be polished to 200um to 250um. integrated module comprises a photoelectric IC 200, an electronic IC 300 and an intermediate layer 400. The intermediate layer 400 includes the TSV 400 and be used as the photo IC 200, electronic IC 300 and base 100 (supporting material) between bridge plate of low cost. the intermediate layer of the smaller pitch on the IC bridging to the substrate (e.g., printed circuit board) on connection pads with larger pitch. The photoelectric IC 200 comprises a light element on a first surface 202 (e.g., light detector) and the pad 220. According to some embodiments, the photo IC 200 can further comprises setting OTSV at the second face (back face) 250, the second surface is opposite the first surface (front surface). OTSV 250 is coupled to the optical element 202. According to some embodiments, if no OTSV, and also can be the photoelectric element surface with an antireflective coating layer (ARC layer), such that the light is effectively coupled to the back. According to some embodiments, photoelectric IC 200 may be disposed on the intermediate layer 400 and electrical pads 220 electrically coupled to the TSV 400. electronic IC 300 is also disposed on the interposer 400 and electrical pad 320 electrically coupled to TSV 400. intermediate layer 400 through a bonding mechanism (e.g. solder balls or copper pillar (130) is disposed on the base plate 100. According to some embodiments, an optical fiber (not shown) can be inserted into OTSV 250 and through OTSV 250 and is aligned with the optical elements 202. ray is incident and by substantially vertical first surface direction, and is incident to the optical element 202 by the OTSV 250 or ARC layer (covering the silicon substrate back surface). According to some embodiments, the optical element may be a light detector and converting the received light into an electrical signal. This electric signal via pad 220, TSV 440 (winding) and inside electric pads 320 so as to transmit to the electronic IC 300. The optical structure of the device of Chen includes the structure and components of the claims, including the method steps for manufacturing the components (see Fig. 15A-C). Response to Arguments Applicant's arguments filed 4/15/26 have been fully considered but they are not persuasive. See examiner remarks. Remarks: In response to the applicant’s argument that the prior art (Chen, CN 104766903) fails to disclose forming a concave surface in the support material through the first mask and bonding the first mask to a bonding layer over an optical interposer, the examiner respectfully disagrees. the prior art teaches forming a method of integrated module, comprising: a first semiconductor substrate forms a surface projection structure and a first power pad; a second semiconductor substrate forms a concave surface structure and a second electrical pad, the first semiconductor substrate to the second semiconductor substrate and the bump on the surface structure is substantially matched with the hollowed structure on aluminum sheet surface, and is electrically connected to the first pad and the second pad are aligned, the applying comprises heating. pressing or a combination of chemical or physical force to engage the first semiconductor substrate and the second semiconductor substrate (see claim 18 and summary of the invention). The prior art teaches using silicon via TSV interposer (440) with a light element 202, at least mask 200/300, and a bonding layer 130 (see Fig. 3). The applicant’s arguments are not persuasive. Refer to the rejection above. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL ST CYR whose telephone number is (571)272-2407. The examiner can normally be reached M to F 8:00-8:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael G Lee can be reached at 571-272-2398. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DANIEL ST CYR Primary Examiner Art Unit 2876 /DANIEL ST CYR/ Primary Examiner, Art Unit 2876
Read full office action

Prosecution Timeline

Mar 20, 2023
Application Filed
Dec 18, 2025
Non-Final Rejection mailed — §102
Apr 15, 2026
Response Filed
May 01, 2026
Final Rejection mailed — §102
Jul 01, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
81%
Grant Probability
95%
With Interview (+13.4%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1409 resolved cases by this examiner. Grant probability derived from career allowance rate.

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