DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/6/26 has been entered.
Election/Restrictions
Applicant’s election without traverse to the restriction requirement mailed on 10/23/25 of Group II (device claims), species T1 (top view shown in Fig. 4F), and subspecies S1 (side view shown in Fig. 10A) in the reply filed on 12/10/25 was acknowledged in a previous office action mailed on 2/18/26. Claims 4, 7-8, 12, and 15-17 are withdrawn.
Foreign Priority
As noted previously: Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5-6, 9, 13-14, and 20-22 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2021/0125642 A1 (“Mariani”).
Mariani teaches, for example:
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Mariani teaches:
1. A method for manufacturing a semiconductor device (see e.g. Figs. 1-2A and accompanying text), comprising:
forming a plurality of transistors (see e.g. para 17) that are arranged in an array in an X-Y plane, each of the transistors including a channel (24, within semiconductor material 18, see e.g. 16) extending in a Z direction (Z-direction as shown in Fig. 2A);
forming a plurality of word lines (e.g. 28, see e.g. para 19) extending in an X direction (X-direction as shown in Fig. 1), each of which electrically connects neighboring some of the transistors at lateral walls of the channels thereof (see e.g. Fig. 2A and para 22, wherein the semiconductor material 18 at channel 24 electrically connects to wordlines 28),
the neighboring some of the transistors being arranged in a column in the X direction; and
forming one or more electromagnetic shielding elements (e.g. 36), including an electromagnetic shielding element (e.g. middle 36 in Fig. 1) extending in the X direction (Fig. 1) and disposed between neighboring two transistors of the transistors that are disposed in a row in a Y direction (e.g. the leftmost 18s, immediately above and below the middle 36, in Fig. 1Y-direction as shown in Fig. 1),
wherein along the Y direction, the channel of each of the neighboring two transistors is disposed between the electromagnetic shielding element and a respective word line of the plurality of word lines electrically connecting that transistor (see Fig. 1).
5. The method of claim 1, wherein each of the channels of the transistors is rectangular pillar-shaped (see e.g. Fig. 2A), and each of the word lines is formed at a lateral wall of a corresponding one of the rectangular pillar-shaped channels (see e.g. Figs. 1 and 2A).
6. The method of claim 5, wherein the lateral walls of the rectangular pillar-shaped channels of the neighboring two transistors at which the word lines are formed face opposite directions (see e.g. Figs. 1 and 2A).
9. A semiconductor device (see e.g. Figs. 1-2A and accompanying text), comprising:
a plurality of transistors (see e.g. para 17) that are arranged in an array in an X-Y plane, each of the transistors including a channel (24, within semiconductor material 18, see e.g. 16) extending in a Z direction (Z-direction as shown in Fig. 2A);
a plurality of word lines (e.g. 28, see e.g. para 19) extending in an X direction (X-direction as shown in Fig. 1), each of which electrically connects neighboring some of the transistors that are arranged in a column in the X direction at lateral walls of the channels thereof (see e.g. Fig. 2A and para 22, wherein the semiconductor material 18 at channel 24 electrically connects to wordlines 28); and
one or more electromagnetic shielding elements (e.g. 36, see para 23), including an electromagnetic shielding element (e.g. middle 36 in Fig. 1) extending in the X direction (Fig. 1) and is disposed between neighboring two transistors of the transistors that are disposed in a row in a Y direction (e.g. the leftmost 18s, immediately above and below the middle 36, in Fig. 1Y-direction as shown in Fig. 1),
wherein along the Y direction, the channel of each of the neighboring two transistors is disposed between the electromagnetic shielding element and a respective word line of the plurality of word lines electrically connecting that transistor (see e.g. Fig. 1).
13. The semiconductor device of claim 9, wherein each of the channels of the transistors is rectangular pillar-shaped (see e.g. Fig. 2A), and each of the word lines is formed at a lateral wall of a corresponding one of the rectangular pillar-shaped channels (see e.g. Figs. 1 and 2A).
14. The semiconductor device of claim 13, wherein the lateral walls of the rectangular pillar-shaped channels of the neighboring two transistors on which the word lines are formed face opposite directions (see e.g. Figs. 1 and 2A).
20. A memory system, comprising:
a semiconductor device (see e.g. Figs. 1-2A and accompanying text), including:
a plurality of transistors (see e.g. para 17) that are arranged in an array in an X-Y plane, each of the transistors including a channel (24, within semiconductor material 18, see e.g. 16) extending in a Z direction (Z-direction as shown in Fig. 2A);
a plurality of word lines (e.g. 28, see e.g. para 19) extending in an X direction (X-direction as shown in Fig. 1), each of which electrically connects neighboring some of the transistors that are arranged in a column in the X direction at lateral walls of the channels thereof (see e.g. Fig. 2A and para 22, wherein the semiconductor material 18 at channel 24 electrically connects to wordlines 28); and
one or more electromagnetic shielding elements (e.g. 36), including an electromagnetic shielding element (e.g. middle 36 in Fig. 1) extending in the X direction (Fig. 1) and disposed between neighboring two transistors of the transistors that are disposed in a row in a Y direction (e.g. the leftmost 18s, immediately above and below the middle 36, in Fig. 1Y-direction as shown in Fig. 1); and
control circuitry coupled to the semiconductor device, the control circuitry configured for controlling operations of the semiconductor device (see e.g. para 22, 39, 59),
wherein along the Y direction, the channel of each of the neighboring two transistors is disposed between the electromagnetic shielding element and a respective word line of the plurality of word lines electrically connecting that transistor (see e.g. Fig. 1).
21. The memory system of claim 20, wherein the control circuitry is further configured to: apply a first voltage to at least one of the electromagnetic shielding elements (shield-connection-line 40 is connected to the shield lines, see e.g. para 27, and as such the control circuitry would be configured to apply a voltage through 40 to 36); and
apply a second voltage that is greater than the first voltage to one of the channels that corresponds to the at least one of the electromagnetic shielding elements (the wordlines 28 are not connected to the shield lines, see e.g. Fig. 1, and therefor the control circuitry would be configured to independently apply voltages to 36 and to 28; as such, it is capable of applying a larger voltage to a channel than to a shielding element).
22. The memory system of claim 20, wherein the control circuitry is further configured to: apply a voltage to at least one of the electromagnetic shielding elements such that a first transistor of the neighboring two transistors, between which the electromagnetic shielding element is disposed, is less affected by a combination of a first electromagnetic field generated by the electromagnetic shielding element with a second electromagnetic field generated by a second transistor of the neighboring two transistors than affected by the second electromagnetic field (the geometry as shown in Fig. 1 is the same relative geometry that is claimed in claims 20 and 22, having a word line, then a channel, then a shield, then a channel, then a word line, in the Y-direction; furthermore, as discussed in claim 21, the word line and the shielding elements may be independently electrically contacted; thus, because the geometry is the same as claimed, and independent voltages may be applied and any desired levels, the disclosed device would be configured to meet the claimed limitations of claim 22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 and 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mariani in view of US 2020/0295008 A1 (“Tang”).
Re claims 2 and 10, Mariani teaches the limitations of claims 1 and 9, respectively, as discussed above, and further teaches wherein each of the transistors further includes a source disposed on a first end of the channel and a drain disposed on a second end of the channel (see e.g. 20 at the bottom end, and 22 at the top end, in Fig. 2; see also para 22).
Mariani does not explicitly further teach that the electromagnetic shielding element has a projection onto the channel in the Y direction that does not overlap the source and the drain.
Tang teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Mariani that the electromagnetic shielding element (e.g. 42 or 43, Fig. 6) has a projection onto the channel 14 in the Y direction that does not overlap the source and the drain (42 has a bottom that is higher than 20 and has a top that is lower than 22, see e.g. Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Tang, including the relative dimensions of the shielding element with respect to the channels, sources, and drains, to the invention of Mariani. The motivation to do so is that the combination produces the predictable results of providing shielding elements that partially fill a line trench while having additional insulating material therein (see e.g. para 52), forming a “plate” structure (see e.g. para 78), to which desired voltages may be provided for desired functions (see e.g. para 78).
Applicant has not disclosed that the claimed relative sizes are for a particular unobvious purpose, produces an unexpected result, or is otherwise critical. It has been found that mere changes in the size of an object, lacking any convincing proof of criticality or unobviousness thereof, is not sufficient for patentability. See e.g. MPEP 2144.04; in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); in re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984);
To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See e.g. MPEP 716.02(b); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Re claims 3 and 11, Mariani teaches the limitations of claims 1 and 9, respectively, as discussed above, but does not expliclty teach wherein the electromagnetic shielding element is shorter in the Z direction than the channels of the neighboring two transistors.
Tang teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Mariani wherein the electromagnetic shielding element (e.g. 42 or 43, Fig. 6) is shorter in the Z direction than the channels of the neighboring two transistors (42 has a bottom that is higher than 20 and has a top that is lower than 22, see e.g. Fig. 6; thus the shield 42 is shower than the channel 14, see e.g. Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Tang, including the relative dimensions of the shielding element with respect to the channels, sources, and drains, to the invention of Mariani. The motivation to do so is that the combination produces the predictable results of providing shielding elements that partially fill a line trench while having additional insulating material therein (see e.g. para 52), forming a “plate” structure (see e.g. para 78), to which desired voltages may be provided for desired functions (see e.g. para 78).
Applicant has not disclosed that the claimed relative sizes are for a particular unobvious purpose, produces an unexpected result, or is otherwise critical. It has been found that mere changes in the size of an object, lacking any convincing proof of criticality or unobviousness thereof, is not sufficient for patentability. See e.g. MPEP 2144.04; in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); in re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984);
To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See e.g. MPEP 716.02(b); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
