Listed by the USPTO as PARENDO, KEVIN A
Tech Center 2800 • Art Units: 2819 2823 2896
This examiner grants 72% of resolved cases
This record covers 773 resolved cases in Tech Center 2800 and Art Unit 2819. The allowance rate is 72.3%, and the median time to allowance is 991 days. Interview lift is 11.5%, showing a positive but limited association between interviews and allowance outcomes.
The leading companies are Samsung Electronics Co., Ltd., Sony Group Corporation, and The Regents of the University of Michigan. The leading firms are HARNESS, DICKEY & PIERCE, P.L.C., MAIER & MAIER, PLLC, and OBLON, MCCLELLAND, MAIER & NEUSTADT, L.L.P. The resolved-case volume supports using these metrics as a practical guide for prosecution planning.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18732713 | TRANSISTOR DEVICE HAVING GATE STRUCTURE WITH ISOLATION REGION THEREIN, AND RELATED FABRICATION METHOD | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18489224 | SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING SEMICONDUCTOR DEVICE | Final Rejection | Samsung Electronics Co., Ltd. |
| 18532449 | WIRING STRUCTURE OF TRANSISTOR FOR DRIVING A DISPLAY PANEL AND A DISPLAY DRIVER IC INCLUDING THE SAME | Final Rejection | LX SEMICON CO., LTD. |
| 18703499 | MICRO-NETWORK INTERCONNECTED NANOSTRUCTURES | Non-Final OA | The Regents of the University of Michigan |
| 18569162 | ELECTRON OVERFLOW OF AIGaN DEEP ULTRAVIOLET LIGHT EMITTING DIODES | Non-Final OA | THE REGENTS OF THE UNIVERSITY OF MICHIGAN |
| 18736288 | THIN FILM TRANSISTOR SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS COMPRISING THE SAME | Non-Final OA | LG Display Co., Ltd. |
| 18489076 | DISPLAY PANEL AND METHOD OF MANUFACTURING DISPLAY PANEL | Final Rejection | Samsung Display Co., Ltd. |
| 18702264 | IMAGING DEVICE | Non-Final OA | SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
| 18549450 | SOLID-STATE IMAGING DEVICE | Final Rejection | SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
| 18257926 | IMAGING ELEMENT AND IMAGING DEVICE | Non-Final OA | SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
| 17707536 | GROOVED PACKAGE | Final Rejection | Intel Corporation |
| 18489172 | PHASE CHANGE RAM DEVICE AND METHOD FOR FABRICATING THE SAME | Final Rejection | Korea Advanced Institute of Science and Technology |
| 18400697 | HYBRID BONDING WITH SONIC ENERGY | Non-Final OA | Adeia Semiconductor Bonding Technologies Inc. |
| 18044780 | METHOD OF PATTERNING A LAYER OF SUPERCONDUCTOR MATERIAL | Final Rejection | Microsoft Technology Licensing, LLC |
| 18182765 | SEMICONDUCTOR STORAGE DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE, AND SEMICONDUCTOR WAFER | Non-Final OA | Kioxia Corporation |
| 18182529 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Non-Final OA | Kioxia Corporation |
| 18732584 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF | Non-Final OA | MEDIATEK INC. |
| 18663724 | ELECTRONIC STRUCTURE INCLUDING DIE WITH BACKSIDE POWER DELIVERY | Non-Final OA | International Business Machines Corporation |
| 18768582 | Semiconductor Devices and Methods for Manufacturing Thereof | Non-Final OA | Infineon Technologies AG |
| 18186441 | SEMICONDUCTOR DEVICES HAVING SHIELDING ELEMENT | Non-Final OA | Yangtze Memory Technologies Co., Ltd. |
| 18733387 | SEMICONDUCTOR DEVICE AND METHODS OF FORMATION | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18744946 | MEMORY DEVICE HAVING MEMORY CELL WITH REDUCED PROTRUSION | Final Rejection | NANYA TECHNOLOGY CORPORATION |
| 18413837 | LIGHT-EMITTING PACKAGE | Final Rejection | SEOUL VIOSYS CO., LTD. |
| 18149210 | PATTERNING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE | Non-Final OA | CHANGXIN MEMORY TECHNOLOGIES, INC. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy72.3% of resolved applications examined by Kevin A Parendo were allowed (773 resolved cases), compared with 69.7% across Art Unit 2819 over the last five years.
This examiner's interview lift is +11.5 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Kevin A Parendo took 991 days on average from filing to allowance.
Kevin A Parendo examines applications in Art Unit 2819 in Tech Center 2800 (Semiconductors, Circuits & Optics).
