DETAILED ACTION
Election/Restrictions - NO TRAVERSE
A restriction requirement was mailed on 10/23/25.
Applicant’s election without traverse of Group II (device claims), species T1 (top view shown in Fig. 4F), and subspecies S1 (side view shown in Fig. 10A) in the reply filed on 12/10/25 is acknowledged. While Applicant noted the election of “Group I”, that is clearly a typographical error because Applicant wrote out “drawn to devices” and identified them as “claims 9-20” (see remarks, filed 12/10/25), so the Office interprets the election as intending Group II, as noted above.
Claims 4, 7-8, 12, and 15-17 are withdrawn. The reasons are as follows:
Claim 8 is in Group I (method claims) and is not linking to Groups I and II, as it contains many purely “method” limitations;
Claims 4 and 12 require the shielding element to be “further disposed between neighboring two of the transistors that are disposed in the column” which only appear to be shown in Figs. 11B and 11E wherein 1008B and 1008E extend between transistors in different rows and columns; Rather, in the elected embodiment of Fig. 4F, 408 merely runs in the x-direction to separate transistors in adjacent columns from each other but does not ever run in the y-direction to separate rows of transistors 401 from each other.
Claims 7 and 15 require electromagnetic shielding contacts pads which are not shown in Figs. 4F and/or 10A;
Claim 16 recites the limitation “at least one of the electromagnetic shielding elements includes a plurality of electromagnetic shielding segments that are separated from one another”. This is shown in non-elected embodiments such as in Fig. 6E (wherein two 608s are nearer each other and run parallel in the x-direction), Fig. 10G (wherein three 1008Gs are stacked, but separate from each other), Fig. 10H (wherein two 1008H are next to each other and run parallel in the x-direction), Fig. 11C (wherein 1008C are in distinct portions running in the x-direction); Fig. 11D (wherein 1008A has separate segments, each running in the Y-direction, wherein the segments are spaced from each other in the x-direction). Rather, the elected invention of Fig. 4F has a single, continuous 408 that does not have distinct segments, which separate nearest neighboring transistors 401 from each other. Claim 17 depend from claim 16.
Claim Objections
Claims 1, 9, and 20 are objected to because “Z direction”, “X direction”, and “Y direction” should be “a Z direction”, “an X direction”, and “a Y direction” in order to have proper antecedent basis.
Claims 2 and 10 are objected to because “Y direction” should be “the Y direction” in order to have proper antecedent basis.
Claims 3 and 11 are objected to because “Z direction” should be “the Z direction” in order to have proper antecedent basis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 18-19 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claim 18 recites the limitation “The semiconductor device of claim 9, wherein at least one of the electromagnetic shielding elements is applied with a first voltage that is less than a second voltage applied to a corresponding one of the channels.”
The metes and bounds of the claimed limitation can not be determined for the following reasons: the claim is indefinite because the claim recites an apparatus but also further includes a method of using the apparatus. A claim that includes both an apparatus and a method of using the apparatus is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the semiconductor device is created as an apparatus or when the semiconductor device is used.
Claim 19 recites the limitation “The semiconductor device of claim 9, wherein at least one of the electromagnetic shielding elements is applied with a voltage such that a first transistor of the neighboring two transistors, between which the electromagnetic shielding element is disposed, is less affected by a combination of a first electromagnetic field generated by the electromagnetic shielding element with a second electromagnetic field generated by a second transistor of the neighboring two transistors than affected by the second electromagnetic field.”
The metes and bounds of the claimed limitation can not be determined for the following reasons: the claim is indefinite because the claim recites an apparatus but also further includes a method of using the apparatus. A claim that includes both an apparatus and a method of using the apparatus is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the semiconductor device is created as an apparatus or when the semiconductor device is used.
Claim Interpretation
For the purposes of examination the process limitations of claims 18 and 19 will be treated as intended result limitations (i.e. the apparatus must be capable of being used for the processes).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6, 9-11, 13-14, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2020/0295008 A1 (“Tang”).
Tang teaches, for example:
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Tang teaches:
1. A method for manufacturing a semiconductor device, comprising:
forming a plurality of transistors (comprising e.g. semiconductor material 14 having source/drain regions 20 and 22 and channel 25 therein, see e.g. para 38 and 72) that are arranged in an array in an X-Y plane, each of the transistors including a channel extending in a Z direction (the semiconductor material of the transistors can be seen in an array in a X-Y plane of e.g. Figs. 4 and Fig. 6, with the long axis of the channel extending in the Z-direction);
forming a plurality of word lines (e.g. 58, see Figs. 6 and 6A), each of which electrically connects neighboring some of the transistors at lateral walls of the channels thereof (see e.g. para 72), the neighboring some of the transistors being arranged in a column in an X direction (see transistors in 2-D arrays in the plans having Q, Y, and X in e.g. Figs. 4 and 6); and
forming one or more electromagnetic shielding elements (e.g. shield material 42 that may be shield plates 43, see e.g. para 61 and 69), at least one of which is disposed between neighboring two of the transistors that are disposed in a row in a Y direction (see e.g. Figs. 6 and 6A).
2. The method of claim 1, wherein
each of the transistors further includes a source (e.g. one of 20 or 22, such as 20, which contacts bitline 18, see e.g. Fig. 14) disposed on a first end (e.g. bottom end) of the channel and a drain (e.g. the other of 20 or 22 not being interpreted as the source, such as 22, see e.g. Fig. 14) disposed on a second end (e.g. top end) of the channel, and
the electromagnetic shielding element has a projection onto the channel in Y direction that does not overlap the source and the drain (see e.g. Fig. 6, wherein shielding material 42 forming shield plate 43 is above 20 and below 22 in the Z-direction).
3. The method of claim 1, wherein the electromagnetic shielding element is shorter in Z direction than the channels of the neighboring two transistors (see e.g. Fig. 6, wherein shielding material 42 forming shield plate 43 is above 20 and below 22 in the Z-direction, thus being shorter than the channel 24).
5. The method of claim 1, wherein each of the channels of the transistors is rectangular pillar-shaped (each is a pillar, as can be seen in e.g. Figs. 6 and 6A; each has at least one rectangular surface as can be seen in Fig. 6), and each of the word lines is formed at a lateral wall of a corresponding one of the rectangular pillar-shaped channels (see e.g. Fig. 6A).
6. The method of claim 5, wherein the lateral walls of the rectangular pillar-shaped channels of the neighboring two transistors at which the word lines are formed face opposite directions (see e.g. Fig. 6A).
9. A semiconductor device, comprising:
a plurality of transistors (comprising e.g. semiconductor material 14 having source/drain regions 20 and 22 and channel 25 therein, see e.g. para 38 and 72) that are arranged in an array in an X-Y plane, each of the transistors including a channel extending in a Z direction (the semiconductor material of the transistors can be seen in an array in a X-Y plane of e.g. Figs. 4 and Fig. 6, with the long axis of the channel extending in the Z-direction);
a plurality of word lines (e.g. 58, see Figs. 6 and 6A), each of which electrically connects neighboring some of the transistors (see e.g. para 72) that are arranged in a column in X direction at lateral walls of the channels thereof (see transistors in 2-D arrays in the plans having Q, Y, and X in e.g. Figs. 4 and 6); and
one or more electromagnetic shielding elements (e.g. shield material 42 that may be shield plates 43, see e.g. para 61 and 69), at least one of which is disposed between neighboring two of the transistors that are disposed in a row in a Y direction (see e.g. Figs. 6 and 6A).
10. The semiconductor device of claim 9, wherein
each of the transistors further includes a source (e.g. one of 20 or 22, such as 20, which contacts bitline 18, see e.g. Fig. 14) disposed on a first end (e.g. bottom end) of the channel and a drain (e.g. the other of 20 or 22 not being interpreted as the source, such as 22, see e.g. Fig. 14) disposed on a second end (e.g. top end) of the channel, and
the electromagnetic shielding element has a projection onto the channel in Y direction that does not overlap the source and the drain (see e.g. Fig. 6, wherein shielding material 42 forming shield plate 43 is above 20 and below 22 in the Z-direction).
11. The semiconductor device of claim 9, wherein the electromagnetic shielding element is shorter in Z direction than the channels of the neighboring two transistors (see e.g. Fig. 6, wherein shielding material 42 forming shield plate 43 is above 20 and below 22 in the Z-direction, thus being shorter than the channel 24).
13. The semiconductor device of claim 9, wherein each of the channels of the transistors is rectangular pillar-shaped (each is a pillar, as can be seen in e.g. Figs. 6 and 6A; each has at least one rectangular surface as can be seen in Fig. 6), and each of the word lines is formed at a lateral wall of a corresponding one of the rectangular pillar-shaped channels (see e.g. Fig. 6A).
14. The semiconductor device of claim 13, wherein the lateral walls of the rectangular pillar-shaped channels of the neighboring two transistors on which the word lines are formed face opposite directions (see e.g. Fig. 6A).
18. The semiconductor device of claim 9, wherein at least one of the electromagnetic shielding elements is applied with a first voltage that is less than a second voltage applied to a corresponding one of the channels (the shielding elements and the channels are not directly electrically connected, having a gate dielectric therebetween, and thus the disclosed device is capable of meeting the claimed limitations including having the claimed voltages applied to the channel and to the shielding element; see also e.g. para 150).
19. The semiconductor device of claim 9, wherein at least one of the electromagnetic shielding elements is applied with a voltage such that a first transistor of the neighboring two transistors, between which the electromagnetic shielding element is disposed, is less affected by a combination of a first electromagnetic field generated by the electromagnetic shielding element with a second electromagnetic field generated by a second transistor of the neighboring two transistors than affected by the second electromagnetic field (structure has the shielding elements between the first and second transistors, as required; the electromagnetic fields generated by the shield and first transistor and by the shield and the second transistor will depend on the voltages applied to the transistors; hence the disclosed device has a geometry that is capable of meeting the claimed invention during use thereof; see also e.g. para 150).
20. A memory system, comprising:
a semiconductor device, including:
a plurality of transistors (comprising e.g. semiconductor material 14 having source/drain regions 20 and 22 and channel 25 therein, see e.g. para 38 and 72) that are arranged in an array in an X-Y plane, each of the transistors including a channel extending in a Z direction (the semiconductor material of the transistors can be seen in an array in a X-Y plane of e.g. Figs. 4 and Fig. 6, with the long axis of the channel extending in the Z-direction);
a plurality of word lines (e.g. 58, see Figs. 6 and 6A), each of which electrically connects neighboring some of the transistors (see e.g. para 72) that are arranged in a column in X direction at lateral walls of the channels thereof (see transistors in 2-D arrays in the plans having Q, Y, and X in e.g. Figs. 4 and 6); and
one or more electromagnetic shielding elements (e.g. shield material 42 that may be shield plates 43, see e.g. para 61 and 69), at least one of which is disposed between neighboring two of the transistors that are disposed in a row in a Y direction (see e.g. Figs. 6 and 6A); and
control circuitry coupled to the semiconductor device, the control circuitry configured for controlling operations of the semiconductor device (see e.g. para 154).
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896