DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1-3, 5-6, 9-11, 13-14, and 20-22 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter (i.e. “new matter") which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 9, and 20 have been amended to include the limitation “wherein one of the electromagnetic shielding elements and each of two of the word lines, between which the one of the electromagnetic shielding elements is disposed, are disposed at opposite lateral walls of one of two of the channels that correspond to the two of the word lines.” This limitation is not disclosed in the originally-filed specification and is thus new matter.
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The elected embodiment (that of Fig. 4F) will be discussed. For example, having added element numbers to correspond with the elements in Figure 4F, the limitation is: wherein one of the electromagnetic shielding elements (408) and each of two of the word lines (407), between which the one of the electromagnetic shielding elements is disposed, are disposed at opposite lateral walls of one of two of the channels (401) that correspond to the two of the word lines.
For the sake of discussion, the following interpretations are used: (1) the “one of the electromagnetic shielding elements” is the left 408, (2) the “two of the word lines, between which the one of the electromagnetic shielding elements is disposed” are the leftmost 407 and second-to-left 407, and (3) the “one of two of the channels” is the 401 in the upper left corner (hereinafter “401UC”), and the “opposite lateral walls” of 401UC are the left wall of 401UC and the right wall of 401UC.
However, unlike what the claim requires, in this figure, the leftmost 407 is on the left wall of 401UC, left 408 is near (which is tenuous at being “at”) the right wall of 401UC, and the second-to-left 407 is not, in any reasonable way, “at” the left wall of 401UC, because it is separated therefrom by both left 408 and another channel 401.
Similar analysis pertains to the other elements in Fig.4F, and to the other disclosed species of this invention in other figures.
Claims 2-8 and 21-22 depend from claim 1; claims 10-17 depend from claim 9; the dependent claims inherit the deficiencies from the claim(s) from which they depend.
Claims 21 and 22 have been newly added, and did not exist in the originally filed specification. They require
(claim 21): The method of claim 1, further comprising: applying a first voltage to at least one of the electromagnetic shielding elements; and applying a second voltage that is greater than the first voltage to one of the channels that corresponds to the at least one of the electromagnetic shielding elements.
(claim 22): The method of claim 1, further comprising: applying a voltage to at least one of the electromagnetic shielding elements such that a first transistor of the neighboring two transistors, between which the electromagnetic shielding element is disposed, is less affected by a combination of a first electromagnetic field generated by the electromagnetic shielding element with a second electromagnetic field generated by a second transistor of the neighboring two transistors than affected by the second electromagnetic field.
Each depends from claim 1, which requires, in part: “A method for manufacturing a semiconductor device…”
The disclosure as originally filed does not describe application of the voltages required by claims 21 or 22 during the manufacturing of the devices. Rather, the disclosure only discloses application of the voltages during operation of the complete device. For that reason, new claims 21 and 22 contain “new matter” that is not supported by the originally-filed application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-3, 5-6, 9-11, 13-14, and 20-22 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claims 1, 9, and 20 recite the limitation “wherein one of the electromagnetic shielding elements and each of two of the word lines, between which the one of the electromagnetic shielding elements is disposed, are disposed at opposite lateral walls of one of two of the channels that correspond to the two of the word lines.”
The metes and bounds of the claimed limitation can not be determined for the following reasons: as discussed in the 112(a) rejection, the disclosed elements do not meet the requirements of each being “at” the opposing lateral sidewalls of “one” channel. The limitation is convoluted and unclear. For example, it is unclear how three elements (one shielding element, two word lines) can each be at two “opposite lateral walls” (which is implied by “opposite”) of “one” channel.
Claims 2-8 and 21-22 depend from claim 1; claims 10-17 depend from claim 9; the dependent claims inherit the deficiencies from the claim(s) from which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6, 9-11, 13-14, and 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2020/0295008 A1 (“Tang”).
Tang teaches, for example:
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Tang teaches:
1. A method for manufacturing a semiconductor device, comprising:
forming a plurality of transistors (comprising e.g. semiconductor material 14 having source/drain regions 20 and 22 and channel 25 therein, see e.g. para 38 and 72) that are arranged in an array in an X-Y plane, each of the transistors including a channel extending in a Z direction (the semiconductor material of the transistors can be seen in an array in a X-Y plane of e.g. Figs. 4 and Fig. 6, with the long axis of the channel extending in the Z-direction);
forming a plurality of word lines (e.g. 58, see Figs. 6 and 6A), each of which electrically connects neighboring some of the transistors at lateral walls of the channels thereof (see e.g. para 72), the neighboring some of the transistors being arranged in a column in an X direction (see transistors in 2-D arrays in the plans having Q, Y, and X in e.g. Figs. 4 and 6); and
forming one or more electromagnetic shielding elements (e.g. shield material 42 that may be shield plates 43, see e.g. para 61 and 69), at least one of which is disposed between neighboring two of the transistors that are disposed in a row in a Y direction (see e.g. Figs. 6 and 6A),
wherein one of the electromagnetic shielding elements and each of two of the word lines, between which the one of the electromagnetic shielding elements is disposed, are disposed at opposite lateral walls of one of two of the channels that correspond to the two of the word lines (see the rejections under 102(a) and 102(b), above. Because the specification does not support this limitation, and its meaning is unclear, it is reasonable to interpret that the geometry shown by Tang in e.g. Figs. 6 and 6A meets the claimed limitation, in light of the specification, wherein “at a sidewall” must be treated broadly and more in the light of “on a side somewhat near a sidewall” and does not preclude other elements from being between the element and the sidewall).
2. The method of claim 1, wherein
each of the transistors further includes a source (e.g. one of 20 or 22, such as 20, which contacts bitline 18, see e.g. Fig. 14) disposed on a first end (e.g. bottom end) of the channel and a drain (e.g. the other of 20 or 22 not being interpreted as the source, such as 22, see e.g. Fig. 14) disposed on a second end (e.g. top end) of the channel, and
the electromagnetic shielding element has a projection onto the channel in Y direction that does not overlap the source and the drain (see e.g. Fig. 6, wherein shielding material 42 forming shield plate 43 is above 20 and below 22 in the Z-direction).
3. The method of claim 1, wherein the electromagnetic shielding element is shorter in the Z direction than the channels of the neighboring two transistors (see e.g. Fig. 6, wherein shielding material 42 forming shield plate 43 is above 20 and below 22 in the Z-direction, thus being shorter than the channel 24).
5. The method of claim 1, wherein each of the channels of the transistors is rectangular pillar-shaped (each is a pillar, as can be seen in e.g. Figs. 6 and 6A; each has at least one rectangular surface as can be seen in Fig. 6), and each of the word lines is formed at a lateral wall of a corresponding one of the rectangular pillar-shaped channels (see e.g. Fig. 6A).
6. The method of claim 5, wherein the lateral walls of the rectangular pillar-shaped channels of the neighboring two transistors at which the word lines are formed face opposite directions (see e.g. Fig. 6A).
9. A semiconductor device, comprising:
a plurality of transistors (comprising e.g. semiconductor material 14 having source/drain regions 20 and 22 and channel 25 therein, see e.g. para 38 and 72) that are arranged in an array in an X-Y plane, each of the transistors including a channel extending in a Z direction (the semiconductor material of the transistors can be seen in an array in a X-Y plane of e.g. Figs. 4 and Fig. 6, with the long axis of the channel extending in the Z-direction);
a plurality of word lines (e.g. 58, see Figs. 6 and 6A), each of which electrically connects neighboring some of the transistors (see e.g. para 72) that are arranged in a column in X direction at lateral walls of the channels thereof (see transistors in 2-D arrays in the plans having Q, Y, and X in e.g. Figs. 4 and 6); and
one or more electromagnetic shielding elements (e.g. shield material 42 that may be shield plates 43, see e.g. para 61 and 69), at least one of which is disposed between neighboring two of the transistors that are disposed in a row in a Y direction (see e.g. Figs. 6 and 6A),
wherein one of the electromagnetic shielding elements and each of two of the word lines, between which the one of the electromagnetic shielding elements is disposed, are disposed at opposite lateral walls of one of two of the channels that correspond to the two of the word lines (see the rejections under 102(a) and 102(b), above. Because the specification does not support this limitation, and its meaning is unclear, it is reasonable to interpret that the geometry shown by Tang in e.g. Figs. 6 and 6A meets the claimed limitation, in light of the specification, wherein “at a sidewall” must be treated broadly and more in the light of “on a side somewhat near a sidewall” and does not preclude other elements from being between the element and the sidewall).
10. The semiconductor device of claim 9, wherein
each of the transistors further includes a source (e.g. one of 20 or 22, such as 20, which contacts bitline 18, see e.g. Fig. 14) disposed on a first end (e.g. bottom end) of the channel and a drain (e.g. the other of 20 or 22 not being interpreted as the source, such as 22, see e.g. Fig. 14) disposed on a second end (e.g. top end) of the channel, and
the electromagnetic shielding element has a projection onto the channel in the Y direction that does not overlap the source and the drain (see e.g. Fig. 6, wherein shielding material 42 forming shield plate 43 is above 20 and below 22 in the Z-direction).
11. The semiconductor device of claim 9, wherein the electromagnetic shielding element is shorter in the Z direction than the channels of the neighboring two transistors (see e.g. Fig. 6, wherein shielding material 42 forming shield plate 43 is above 20 and below 22 in the Z-direction, thus being shorter than the channel 24).
13. The semiconductor device of claim 9, wherein each of the channels of the transistors is rectangular pillar-shaped (each is a pillar, as can be seen in e.g. Figs. 6 and 6A; each has at least one rectangular surface as can be seen in Fig. 6), and each of the word lines is formed at a lateral wall of a corresponding one of the rectangular pillar-shaped channels (see e.g. Fig. 6A).
14. The semiconductor device of claim 13, wherein the lateral walls of the rectangular pillar-shaped channels of the neighboring two transistors on which the word lines are formed face opposite directions (see e.g. Fig. 6A).
18. The semiconductor device of claim 9, wherein at least one of the electromagnetic shielding elements is applied with a first voltage that is less than a second voltage applied to a corresponding one of the channels (the shielding elements and the channels are not directly electrically connected, having a gate dielectric therebetween, and thus the disclosed device is capable of meeting the claimed limitations including having the claimed voltages applied to the channel and to the shielding element; see also e.g. para 150).
19. The semiconductor device of claim 9, wherein at least one of the electromagnetic shielding elements is applied with a voltage such that a first transistor of the neighboring two transistors, between which the electromagnetic shielding element is disposed, is less affected by a combination of a first electromagnetic field generated by the electromagnetic shielding element with a second electromagnetic field generated by a second transistor of the neighboring two transistors than affected by the second electromagnetic field (structure has the shielding elements between the first and second transistors, as required; the electromagnetic fields generated by the shield and first transistor and by the shield and the second transistor will depend on the voltages applied to the transistors; hence the disclosed device has a geometry that is capable of meeting the claimed invention during use thereof; see also e.g. para 150).
20. A memory system, comprising:
a semiconductor device, including:
a plurality of transistors (comprising e.g. semiconductor material 14 having source/drain regions 20 and 22 and channel 25 therein, see e.g. para 38 and 72) that are arranged in an array in an X-Y plane, each of the transistors including a channel extending in a Z direction (the semiconductor material of the transistors can be seen in an array in a X-Y plane of e.g. Figs. 4 and Fig. 6, with the long axis of the channel extending in the Z-direction);
a plurality of word lines (e.g. 58, see Figs. 6 and 6A), each of which electrically connects neighboring some of the transistors (see e.g. para 72) that are arranged in a column in X direction at lateral walls of the channels thereof (see transistors in 2-D arrays in the plans having Q, Y, and X in e.g. Figs. 4 and 6); and
one or more electromagnetic shielding elements (e.g. shield material 42 that may be shield plates 43, see e.g. para 61 and 69), at least one of which is disposed between neighboring two of the transistors that are disposed in a row in a Y direction (see e.g. Figs. 6 and 6A); and
control circuitry coupled to the semiconductor device, the control circuitry configured for controlling operations of the semiconductor device (see e.g. para 154),
wherein one of the electromagnetic shielding elements and each of two of the word lines, between which the one of the electromagnetic shielding elements is disposed, are disposed at opposite lateral walls of one of two of the channels that correspond to the two of the word lines (see the rejections under 102(a) and 102(b), above. Because the specification does not support this limitation, and its meaning is unclear, it is reasonable to interpret that the geometry shown by Tang in e.g. Figs. 6 and 6A meets the claimed limitation, in light of the specification, wherein “at a sidewall” must be treated broadly and more in the light of “on a side somewhat near a sidewall” and does not preclude other elements from being between the element and the sidewall).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered. The arguments are moot in view of the new ground(s) of rejection, under 35 USC 112(a) and 112(b).
Regarding the rejections under 35 USC 102 and/or 103, the arguments are not persuasive. Applicant argues that Tang’s channels are not rectangular pillar-shaped (see 4/24/26 remarks, page 9) and Tang does not teach the new limitation of claims 1, 9, or 20. The Offices notes that “rectangular pillar-shaped channels” are not required of these claims. Furthermore, non-rectangular shaped channels can have “opposing” walls, even if they are not parallel. Furthermore, regarding the new language of claims 1, 9, and 20, note the 112(a) and 112(b) rejections, and that in light of the specification, the limitations are unclear and the geometry of Tang reasonably reads thereon.
Conclusion
Conclusion / Finality
Applicant's amendment changed the scope of the claims and necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
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