DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 20 recites the limitation "the RDL" There is insufficient antecedent basis for this limitation in the claim. It is unclear whether the RDL in claims 6 and/or 20 is the same RDL as the “first RDL” defined in parent claims 1 and/or 15 or whether it is a different RDL. For purpose of compact prosecution, the Examiner will use the definition of a “first RDL” in parent claims 1 and/or 15 to be the same “RDL” as recited in claims 6 and 20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 9, 11, 13-19, and 23 is/are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Zhai (US 20160172310 A1).
Regarding claim 1, Zhai teaches an integrated circuit (IC) (Fig. 2-4(1): 240), comprising:
a plurality of metals (Fig. 2-3(3): 230, 234, 222, 224, 245.1, 245.2; 230, 222, 224 are metal layers of layer 240.3 in Fig. 2-4(1); see [0091], [0093]; also, Fig. 2-4(1): 245.1, 245.2 are metal layers of layer 240.2 in Figs. 2-4(1) and 2-2, see [0099], [0085]; alternatively, the metals are 243 & 245.1 & 245.2 ) and a plurality of insulators (Figs. 2-3(3) & 2-4(1): 220, see [0089]; also, Fig. 2-2: 218a, see [0086]) alternatively stacked, a first metal (230; alternatively, 243) being a top most metal (Fig. 2-3(3) shows 230 being a top-most metal of 231; alternatively, 243 is the topmost of 243 & 245.1 & 245.2) among the plurality of metals;
one or more redistribution layers (RDL) (Fig. 2-4(1): 246.1, 246.2; each of these layers is shown in Fig. 2-1(5) as 205.1 & 206.1 & 206.2, see also ¶ 0066 ) above the plurality of metals, a first RDL (246.2) being a bottom most RDL among the one or more RDLs (as shown in Fig. 2-4(1), 246.2 is the bottom most RDL);
one or more interlayer dielectrics (ILD) (Fig. 2-1(5): 205.2 & 205.3) corresponding to each of the one or more RDLs (a corresponding set of 205.2 & 205.3 corresponds to each 246.1 & 246.2 as shown in Fig. 2-4(1) but not labelled), each ILD encapsulating a corresponding RDL (Fig. 2-1(5) shows 205.2 &205.3 encapsulating 205.1 & 206.1 & 206.2) including a first ILD encapsulating the first RDL (Fig. 2-4(1) shows the bottom set of 205.2&205.3 encapsulating bottom 246.2); and
a first airgap (Fig. 2-1(5): 206.3 & 206.4 are insulation spaces, hence are air gaps; also see [0066]) formed in the first ILD under the first RDL (Fig. 2-1(5) shows 206.3 & 206.4 inside 205.3 and under 205.1),
wherein the one or more RDLs are configured as an inductor (¶ 0066: inductive laminate; also see Fig. 2-1(8) and ¶ 0073).
Regarding claim 2, the IC of claim 1, further comprising: a circuit-under-inductor (CUI) (Figs. 2-4(1) & 2-4(2): 240.3a & 240.3b & 240.2 & 243, also see ¶ 0096-0098) vertically below the inductor (Fig. 2-4(1) shows 240.3a & 240.3b & 240.2 under 246.2).
Regarding claim 3, the IC of claim 2, wherein one or more metals of the plurality of metals other than the first metal are configured as the CUI (Fig. 2-4(2) and ¶ 0096-0098 explains ICs 242.3a & 242.3b & capacitor 242.2 in a circuit connected to inductor 242.1; metals 230, 222, 224, 245.1, 245.2 are part of this circuit, as shown in Figs. 2-3(3) and 2-4(1); also see claim 5 rejection wherein first metal 243 is not electrically connected to any element).
Regarding claim 4, the IC of claim 2, wherein the first metal is patterned to vertically overlay the CUI (Figs. 2-3(3) and 2-4(1) show 230, or alternatively 243, on top of and horizontally spanning the CUI elements 240.3a & 240.3b & 240.2 & 243).
Regarding claim 5, the IC of claim 2, wherein the first metal (see alternative metals in claim 1 where 243 is the first metal) is configured to float in voltage (¶ 0098: 243 is bonded to 240.3a & 240.3b using an electrically non-conductive resin; since 243 is not electrically connect to any device, then it is configured to float in voltage).
Regarding claim 9, the IC of claim 1,
wherein the one or more RDLs comprise at least one RDL (Fig. 2-4(1): 246.1, which is represented as 205.1 & 206.1 & 206.2 in Fig. 2-1(5)) above the first RDL encapsulated by corresponding at least one ILD (Fig. 2-1(5): 205.2 & 205.3; Fig. 2-4(1) also shows 205.2 & 205.3, but not labeled, encapsulating 246.1) above the first ILD, and
wherein the IC further comprises a third airgap (Fig. 2-1(5): 206.3 & 206.4 ) formed in the at least one ILD under the at least one RDL (Fig. 2-1(5) shows 206.3 & 206.4 inside 205.3 and under 205.1; 205.1 corresponds to 246.1 in Fig. 2-4(1)).
Regarding claim 11, the IC of claim 1, wherein the one or more RDLs are formed from copper (Cu) (Fig. 2-1(5), ¶ 0066: 206.1 & 206.2 are made of copper).
Regarding claim 13, the IC of claim 1, wherein one or more metals of the plurality of metals other than the first metal are formed from copper (Cu) ( ¶ 0085, ¶ 0089).
Regarding claim 14, the IC of claim 1, wherein the IC is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle (¶ 0002, ¶ 0004 ).
Regarding claim 15, Zhai teaches a method of fabricating an integrated circuit (Fig. 2-4(1): 240), the method comprising:
forming a plurality of metals (Fig. 2-3(3): 230, 234, 222, 224, 245.1, 245.2; 230, 222, 224 are metal layers of layer 240.3 in Fig. 2-4(1); see [0091], [0093]; also, Fig. 2-4(1): 245.1, 245.2 are metal layers of layer 240.2 in Figs. 2-4(1) and 2-2, see [0099], [0085]; alternatively, the metals are 243 & 245.1 & 245.2 ) and a plurality of insulators (Figs. 2-3(3) & 2-4(1): 220, see [0089]; also, Fig. 2-2: 218a, see [0086]) alternatively stacked, a first metal (230; alternatively, 243) alternatively stacked, a first metal being a top most metal (Fig. 2-3(3) shows 230 being a top-most metal of 231; alternatively, 243 is the topmost of 243 & 245.1 & 245.2) among the plurality of metals;
forming one or more redistribution layers (RDL) (Fig. 2-4(1): 246.1, 246.2; each of these layers is shown in Fig. 2-1(5) as 205.1 & 206.5 & 206.6, see also ¶ 0066 ) above the plurality of metals, a first RDL (246.2) being a bottom most RDL among the one or more RDLs (as shown in Fig. 2-4(1), 246.2 is the bottom most RDL);
forming one or more interlayer dielectrics (ILD) (Fig. 2-1(5): 205.2 & 205.3) corresponding to each of the one or more RDLs (a corresponding set of 205.2 & 205.3 corresponds to each 246.1 & 246.2 as shown in Fig. 2-4(1) but not labelled), each ILD encapsulating a corresponding RDL (Fig. 2-1(5) shows 205.2 &205.3 encapsulating 205.1 & 206.5 & 206.6) including a first ILD encapsulating the first RDL (Fig. 2-4(1) shows the bottom set of 205.2&205.3 encapsulating bottom 246.2); and
forming a first airgap (Fig. 2-1(5): 206.3 & 206.4 are insulation spaces, hence are air gaps; also see [0066]) in the first ILD under the first RDL (Fig. 2-1(5) shows 206.3 & 206.4 inside 205.3 and under 205.1),
wherein the one or more RDLs are configured as an inductor (¶ 0066: inductive laminate; also see Fig. 2-1(8) and ¶ 0073).
Regarding claim 16, the method of claim 15, further comprising: forming a circuit-under-inductor (CUI) (Figs. 2-4(1) & 2-4(2): 240.3a & 240.3b & 240.2 & 243, also see ¶ 0096-0098) vertically below the inductor (Fig. 2-4(1) shows 240.3a & 240.3b & 240.2 under 246.2).
Regarding claim 17, the method of claim 16, wherein one or more metals of the plurality of metals other than the first metal are configured as the CUI (Fig. 2-4(2) and ¶ 0096-0098 explains ICs 242.3a & 242.3b & capacitor 242.2 in a circuit connected to inductor 242.1; metals 230, 222, 224, 245.1, 245.2 are part of this circuit, as shown in Figs. 2-3(3) and 2-4(1); also see claim 19 rejection wherein first metal 243 is not electrically connected to any element).
Regarding claim 18, the method of claim 16, wherein the first metal is patterned to vertically overlay the CUI (Figs. 2-3(3) and 2-4(1) show 230, or alternatively 243, on top of and horizontally spanning the CUI elements 240.3a & 240.3b & 240.2 & 243).
Regarding claim 19, the method of claim 16, wherein the first metal (see alternative metals in claim 1 where 243 is the first metal) is configured to float in voltage (¶ 0098: 243 is bonded to 240.3a & 240.3b using an electrically non-conductive resin; since 243 is not electrically connect to any device, then it is configured to float in voltage).
Regarding claim 23, the method of claim 15,
wherein the one or more RDLs comprise at least one RDL (Fig. 2-4(1): 246.1, which is represented as 205.1 & 206.1 & 206.2 in Fig. 2-1(5)) above the first RDL encapsulated by corresponding at least one ILD (Fig. 2-1(5): 205.2 & 205.3; Fig. 2-4(1) also shows 205.2 & 205.3, but not labeled, encapsulating 246.1) above the first ILD, and
wherein the method further comprises forming a third airgap (Fig. 2-1(5): 206.3 & 206.4 ) in the at least one ILD under the at least one RDL (Fig. 2-1(5) shows 206.3 & 206.4 inside 205.3 and under 205.1; 205.1 corresponds to 246.1 in Fig. 2-4(1)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhai (US 20160172310 A1) in view of another embodiment of Zhai.
Regarding claim 7, Zhai teaches the IC of claim 1, which teaches a modular laminate structure to be an inductor (Figs. 2-1(1) to 2-1 (14) and ¶ 0061-¶ 0082; also shown in Fig. 2-4(1) as 240.1 ) having airgaps (Fig. 2-1(5): 206.3 & 206.4) formed in an insulator (206.3 & 206.4) and a modular laminate structure containing the first metal (Fig. 2-3(3): 230) and chips (Figs. 2-3(1) to 2.3(3) and ¶ 0089-¶ 0092; also shown in Fig. 2-4(1) as 240.3) and further teaches that these modular laminate structures can be arranges in any vertical order (¶ 0095).
However, Zhai’s device of claim 1 does not further comprise of a second airgap formed below the first metal.
Zhai, in other embodiments (Figs. 3-10, 3-11(1), and 3-11(3)), further teaches using these modular laminate structures to form the circuits of these embodiments (¶ 0110), wherein each embodiment contains multiple inductors (see L0, L1,.. Ln). Hence, Zhai teaches a second airgap formed in an insulator below the first metal (since a second or third or nth inductive modular structure can be placed under the module structure containing chips).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Zhai into the device of Zhai as described in claim 1 to form a second airgap in an insulator below a first metal in an integrated circuit at least comprising of a plurality of metals and insulators alternatively stacked, with the first metal being a top most metal among the plurality of metals; one or more RDLs above the plurality of metals, a first RDL being a bottom RDL among the one or more RDLs; and a first airgap in a first ILD under the first RDL, wherein the one or more RDLs are configured as an inductor. The ordinary artisan would have been motivated to modify the embodiment of Zhai in claim 1 in the manner set forth above for at least the purpose of manufacturing power managements integrated circuits (Fig. 3-10, ¶ 0120), low noise voltage regulator (Fig. 1-11(1), ¶0121), and multiple output voltage regulator (Fig. 3-11 (3), ¶ 0055, ¶ 0121) using any vertical arrangement of the modular laminate structures (¶ 0095, ¶0110).
Regarding claim 21, Zhai teaches the method of claim 15, which teaches a modular laminate structure to be an inductor (Figs. 2-1(1) to 2-1 (14) and ¶ 0061-¶ 0082; also shown in Fig. 2-4(1) as 240.1 ) having airgaps (Fig. 2-1(5): 206.3 & 206.4) formed in an insulator (206.3 & 206.4) and a modular laminate structure containing the first metal (Fig. 2-3(3): 230) and chips (Figs. 2-3(1) to 2.3(3) and ¶ 0089-¶ 0092; also shown in Fig. 2-4(1) as 240.3) and further teaches that these modular laminate structures can be arranges in any vertical order (¶ 0095).
However, Zhai’s method of claim 15 does not further comprise forming a second airgap below the first metal.
Zhai, in other embodiments (Figs. 3-10, 3-11(1), and 3-11(3)) further teaches using these modular laminate structures to form the circuits of these embodiments (¶ 0110) , wherein each embodiment contains multiple inductors (see L0, L1,.. Ln). Hence, Zhai teaches a second airgap formed in an insulator below the first metal (since a second or third or nth inductive modular structure can be placed under the module structure containing chips).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Zhai into the method of Zhai as described in claim 15 to form a second airgap in an insulator below the first metal in a method of fabricating an integrated circuit at least comprising of forming a plurality of metals and insulators alternatively stacked, with the first metal being a top most metal among the plurality of metals; forming one or more RDLs above the plurality of metals, a first RDL being a bottom RDL among the one or more RDLs; and forming a first airgap in a first ILD under the first RDL, wherein the one or more RDLs are configured as an inductor. The ordinary artisan would have been motivated to modify the method of Zhai in claim 15 in the manner set forth above for at least the purpose of manufacturing power managements integrated circuits (Fig. 3-10, ¶ 0120), low noise voltage regulator (Fig. 1-11(1), ¶0121), and multiple output voltage regulator (Fig. 3-11 (3), ¶ 0055, ¶ 0121) using any vertical arrangement of the modular laminate structures (¶ 0095, ¶0110).
Claim(s) 6, 8, 10, 20, 22, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhai (US 20160172310 A1) and further in view of Zhen (US 6835631 B1).
Regarding claim 6, Zhai teaches the IC of claim 1 but does not teach wherein the first airgap constitutes between 10% and 60% of volume of space within the first ILD below the RDL.
Zhen, in the same field of invention, teaches a device wherein the first airgap (Fig. 5: 28 & 30) constitutes between 10% and 60% (Fig. 5 shows 28 & 30 constitute 10% to 60% of space within 16’ & 14’) of volume of space within the first ILD (16’&14’) below the RDL (34 is an inductor).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zhen into the device of Zhai to make the volume of a first air gap constitute between 10% to 60% of the volume of space within a first ILD below a first RDL in an integrated circuit at least comprising of a plurality of metals and insulators alternatively stacked; one or more RDLs above the plurality of metals, the first RDL being a bottom RDL among the one or more RDLs; the first airgap in the first ILD under the first RDL, wherein the one or more RDLs are configured as an inductor. The ordinary artisan would have been motivated to modify Zhai in the manner set forth above for at least the purpose of optimizing the volume of the first air gap (Zhen. Col. 2, Lns. 65-67 ) relative to the volume of the first ILD layers (Zhen. Col 2, Lns. 20-23 and Lns. 34-37) to achieve a corresponding optimized value of a quality factor of the inductor (Zhen Col. 3, Lns. 40-42) and for reducing the capacitance loss of the inductor and substrate loss due to eddy current (Zhen Col. 3, Lns. 13-19), thereby improving the performance of the inductor.
Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A).
Regarding claim 8, Zhai teaches the IC of claim 7, but does not teach: wherein the second airgap constitutes between 10% and 60% of volume of space within the insulator below the first metal.
Zhen, in the same field of invention, teaches a device wherein the second airgap (Fig. 5: 28 & 30) constitutes between 10% and 60% (Fig. 5 shows 28 & 30 constitute 10% to 60% of space within 16’ & 14’) of volume of space within the insulator (16’&14’) below the first metal (34 is an inductor, which corresponds to Zhen’s second RDL in claim 7 rejection; claim 7 rejection states 34 is under first metal 230; hence Zhai in view of Zhen teaches insulator is below the first metal).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zhen into the device of Zhai to make the volume of a second air gap constitute between 10% to 60% of the volume of space within an insulator below a first metal in an integrated circuit at least comprising of a plurality of metals and insulators alternatively stacked, with the first metal being a top most metal among the plurality of metals; one or more RDLs above the plurality of metals, a first RDL being a bottom RDL among the one or more RDLs; a first airgap in an ILD under a first RDL, wherein the one or more RDLs are configured as an inductor; and the second airgap formed in the insulator below the first metal. The ordinary artisan would have been motivated to modify Zhai in the manner set forth above for at least the purpose of optimizing the volume of the second air gap (Zhen. Col. 2, Lns. 65-67 ) relative to the volume of the insulator below the first metal (Zhen. Col 2, Lns. 20-23 and Lns. 34-37) to achieve a corresponding optimized value of a quality factor of the inductor (Zhen Col. 3, Lns. 40-42) and for reducing the capacitance loss of the inductor and substrate loss due to eddy current (Zhen Col. 3, Lns. 13-19), thereby improving the performance of the inductor.
Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A).
Regarding claim 10, Zhai teaches the IC of claim 9, but does not teach: wherein the third airgap constitutes between 10% and 60% of volume of space within the at least one ILD under the at least one RDL.
Zhen, in the same field of invention, teaches a device wherein the third airgap (Fig. 5: 28 & 30) constitutes between 10% and 60% (Fig. 5 shows 28 & 30 constitute 10% to 60% of space within 16’ & 14’) of volume of space within the at least one ILD (16’&14’) under the at least one RDL (34 is an inductor).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zhen into the device of Zhai to make the volume of a third air gap constitute between 10% to 60% of the volume of space within an at least one ILD under an at least one RDL in an integrated circuit at least comprising of a plurality of metals and insulators alternatively stacked; one or more RDLs above the plurality of metals, a first RDL being a bottom RDL among the one or more RDLs; a first airgap in an ILD under a first RDL, wherein the one or more RDLs are configured as an inductor; wherein the one or more RDLs comprise at least one RDL above the first RDL encapsulated by corresponding at least one ILD above the first ILD, and wherein the integrated circuit further comprises the third air gap formed in the at least one ILD under the at least one RDL. The ordinary artisan would have been motivated to modify Zhai in the manner set forth above for at least the purpose of optimizing the volume of the third air gap (Zhen. Col. 2, Lns. 65-67 ) relative to the volume of the one ILD layers under the at least one RDL (Zhen. Col 2, Lns. 20-23 and Lns. 34-37) to achieve a corresponding optimized value of a quality factor of the inductor (Zhen Col. 3, Lns. 40-42) and for reducing the capacitance loss of the inductor and substrate loss due to eddy current (Zhen Col. 3, Lns. 13-19), thereby improving the performance of the inductor.
Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A).
Regarding claim 20, Zhai the method of claim 15, but does not teach: wherein the first airgap constitutes between 10% and 60% of volume of space within the first ILD below the RDL.
Zhen, in the same field of invention, teaches a method wherein the first airgap (Fig. 5: 28 & 30) constitutes between 10% and 60% (Fig. 5 shows 28 & 30 constitute 10% to 60% of space within 16’ & 14’) of volume of space within the first ILD (16’&14’) below the RDL (34 is an inductor).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zhen into the method of Zhai to make the volume of a first air gap constitute between 10% to 60% of the volume of space within a first ILD below a first RDL in a method of fabricating an integrated circuit at least comprising of forming a plurality of metals and insulators alternatively stacked; forming one or more RDLs above the plurality of metals, the first RDL being a bottom RDL among the one or more RDLs; forming the first airgap in the first ILD under the first RDL, wherein the one or more RDLs are configured as an inductor. The ordinary artisan would have been motivated to modify Zhai in the manner set forth above for at least the purpose of optimizing the volume of the first air gap (Zhen. Col. 2, Lns. 65-67 ) relative to the volume of the first ILD layers (Zhen. Col 2, Lns. 20-23 and Lns. 34-37) to achieve a corresponding optimized value of a quality factor of the inductor (Zhen Col. 3, Lns. 40-42) and for reducing the capacitance loss of the inductor and substrate loss due to eddy current (Zhen Col. 3, Lns. 13-19), thereby improving the performance of the inductor.
Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A).
Regarding claim 22, Zhai the method of claim 21, but does not teach: wherein the second airgap constitutes between 10% and 60% of volume of space within the insulator below the first metal.
Zhen, in the same field of invention, teaches a method wherein the second airgap (Fig. 5: 28 & 30) constitutes between 10% and 60% (Fig. 5 shows 28 & 30 constitute 10% to 60% of space within 16’ & 14’) of volume of space within the insulator (16’&14’) below the first metal (34 is an inductor, which corresponds to Zhen’s second RDL in claim 7 rejection; claim 7 rejection states 34 is under first metal 230; hence Zhai in view of Zhen teaches insulator is below the first metal).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zhen into the method of Zhai to make the volume of a second air gap constitute between 10% to 60% of the volume of space within an insulator below a first metal in a method of fabricating an integrated circuit at least comprising of a forming plurality of metals and insulators alternatively stacked, with the first metal being a top most metal among the plurality of metals; forming one or more RDLs above the plurality of metals, a first RDL being a bottom RDL among the one or more RDLs; forming a first airgap in an ILD under a first RDL, wherein the one or more RDLs are configured as an inductor; and forming the second airgap in the insulator below the first metal. The ordinary artisan would have been motivated to modify Zhai in the manner set forth above for at least the purpose of optimizing the volume of the second air gap (Zhen. Col. 2, Lns. 65-67 ) relative to the volume of the insulator below the first metal (Zhen. Col 2, Lns. 20-23 and Lns. 34-37) to achieve a corresponding optimized value of a quality factor of the inductor (Zhen Col. 3, Lns. 40-42) and for reducing the capacitance loss of the inductor and substrate loss due to eddy current (Zhen Col. 3, Lns. 13-19), thereby improving the performance of the inductor.
Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A).
Regarding claim 24, Zhai the method of claim 23, but does not teach: wherein the third airgap constitutes between 10% and 60% of volume of space within the at least one ILD under the at least one RDL.
Zhen, in the same field of invention, teaches a method wherein the third airgap (Fig. 5: 28 & 30) constitutes between 10% and 60% (Fig. 5 shows 28 & 30 constitute 10% to 60% of space within 16’ & 14’) of volume of space within the at least one ILD (16’&14’) under the at least one RDL (34 is an inductor).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zhen into the method of Zhai to make the volume of a third air gap constitute between 10% to 60% of the volume of space within an at least one ILD under an at least one RDL in a method of fabricating an integrated circuit at least comprising of forming a plurality of metals and insulators alternatively stacked; forming one or more RDLs above the plurality of metals, a first RDL being a bottom RDL among the one or more RDLs; forming a first airgap in an ILD under a first RDL, wherein the one or more RDLs are configured as an inductor; wherein the one or more RDLs comprise at least one RDL above the first RDL encapsulated by corresponding at least one ILD above the first ILD, and wherein the method of fabricating the integrated circuit further comprises forming the third air gap formed in the at least one ILD under the at least one RDL. The ordinary artisan would have been motivated to modify Zhai in the manner set forth above for at least the purpose of optimizing the volume of the third air gap (Zhen. Col. 2, Lns. 65-67 ) relative to the volume of the one ILD layers under the at least one RDL (Zhen. Col 2, Lns. 20-23 and Lns. 34-37) to achieve a corresponding optimized value of a quality factor of the inductor (Zhen Col. 3, Lns. 40-42) and for reducing the capacitance loss of the inductor and substrate loss due to eddy current (Zhen Col. 3, Lns. 13-19), thereby improving the performance of the inductor.
Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2144.05 (II) (A).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhai (US 20160172310 A1), as applied to claims 1, and further in view of Kim (US 20210271275 A1).
Regarding claim 12, Zhai teaches the IC of claim 1, wherein the first metal is formed from copper (¶ 0090). However, Zhai does not teach the first metal can be formed from aluminum (Al).
Kim, in the same field of invention, teaches a device having a metal layer (Fig. 7: 714U or 714L) made of copper or aluminum (¶ 0050).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the copper that comprises the first metal in Zhai with aluminum for the predictable result of providing electrical conductivity (Kim [0050]) or, alternatively, for the purpose of substituting equivalent materials known in the prior art for the same purpose of providing electrical coupling (Kim [0050]).
Conclusion
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/D.Y./Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Examiner, Art Unit 2899