DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot in light of new grounds of rejection made below.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 9-10, 12, 14-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki et al (US 2010/0133571; hereinafter Kawasaki) in view of Ota et al (US 2016/0233396; hereinafter Ota) and Yamamoto et al (US 2020/0343422; hereinafter Yamamoto).
Regarding claim 1, Fig 2 of Kawasaki discloses A light-emitting device, comprising:
a substrate (10; Fig 2; ¶ [0039]) including a first surface (Top surface; Fig 2) and a second surface (Bottom surface; Fig 2) opposite to said first surface, said first surface extending along a first direction (Horizontal Direction; Fig 2) and a second direction (Vertical Direction; Fig 2) intersecting the first direction;
a first chip (1; Fig 2; ¶ [0039]) disposed on said first surface (Top surface; Fig 2) of said substrate (10; Fig 2; ¶ [0039]);
a second chip (2; Fig 2; ¶ [0041]) disposed on said first surface (Top surface; Fig 2) of said substrate (10; Fig 2; ¶ [0039]), and formed with a top surface (Fig 2), a bottom surface (Fig 2) opposite to said top surface, and a plurality of side surfaces that are connected to said top surface and said bottom surface;
a first buffer layer (5/5a; Fig 2; ¶ [0038]) disposed on said top surface (Top surface; Fig 2) of said second chip so as to relieve stress (Since the layer 5/5a comprises the same material as disclosed by the applicant; therefore, buffer layer (5/5a) will disclose the limitation); and
an encapsulating layer (8; Fig 2; ¶ [0051]) made of silicone-containing resin (¶ [0051]) and disposed on said first surface (Top surface; Fig 2) of said substrate to allow said first chip (1; Fig 2; ¶ [0039]), said first buffer layer (5/5a; Fig 2; ¶ [0038]) and said second chip (2; Fig 2; ¶ [0041]) to be encapsulated between said substrate (10; Fig 2; ¶ [0039]) and said encapsulating layer (8; Fig 2; ¶ [0051]),
wherein said substrate (10; Fig 2; ¶ [0039]) has two edges (Left/Right; Fig 1) spaced apart from each other in one of said first direction and said second direction, said first chip (1; Fig 2; ¶ [0039]) having a first minimum distance distant from one of said two edges (Right edge; Fig 1) in one of said first direction and said second direction, said second chip (2; Fig 2; ¶ [0041]) having a second minimum distance distant from one of said two edges (Right edge; Fig 1) in a corresponding one of said first direction and said second direction, said first minimum distance being greater (Fig 1) than said second minimum distance, and
wherein said encapsulating layer (8; Fig 2; ¶ [0051]) is in contact with at least a portion of said first surface (Top surface; Fig 1) of said substrate (10; Fig 2; ¶ [0039]) and a surface of said first buffer layer (5/5a; Fig 2; ¶ [0038]) opposite to said second chip, such that said first buffer layer (5/5a; Fig 2; ¶ [0038]) connects said second chip (2; Fig 2; ¶ [0041]) to said encapsulating layer (8; Fig 2; ¶ [0051]).
However Kawasaki does not expressly disclose the following:
a first chip including a first type semiconductor layer, a second type semiconductor layer, and an active layer that is interposed between said first type semiconductor layer and said second type semiconductor layer and that is configured to emit a light;
an encapsulating layer made of fluorine-containing resin.
In the same field of endeavor, Fig 1 of Ota discloses an encapsulating layer can be made up of silicone containing resin or fluorine containing resin (¶ [0059]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that an encapsulating layer is made up of fluorine containing resin or silicone containing resin for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06).
However Kawasaki in view of Ota does not expressly disclose the following:
a first chip including a first type semiconductor layer, a second type semiconductor layer, and an active layer that is interposed between said first type semiconductor layer and said second type semiconductor layer and that is configured to emit a light.
In the same field of endeavor, Kawasaki discloses a first chip (10; Fig 3; ¶ [0057]) disposed on a first surface (Top surface; Fig 3) of said substrate and including a first type semiconductor layer (¶ [0036]), a second type semiconductor layer (¶ [0036]) and an active layer (¶ [0036]) that is interposed between said first type semiconductor layer and said second type semiconductor layer and that is configured to emit a light (¶ [0036]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a first chip disposed on the substrate includes a first type semiconductor layer, a second type semiconductor layer, and an active layer that is interposed between said first type semiconductor layer and said second type semiconductor layer in order for the light emitting chip to emit light (¶ [0036]).
Regarding claim 2, Fig 2 of Kawasaki discloses said first buffer layer (5/5a; Fig 2; ¶ [0038]) further covers said side surfaces (Fig 2) of said second chip (2; Fig 2; ¶ [0041]).
Regarding claim 5, Fig 2 of Kawasaki discloses said first buffer layer (5/5a; Fig 2; ¶ [0038]) is made of material selected from the group consisting of silicone rubber, epoxy resin (¶ [0038]).
Regarding claim 9, Fig 2 of Kawasaki discloses said second chip (2; Fig 2; ¶ [0041]) is an electrostatic discharge protection chip (¶ [0036]).
Regarding claim 10, (In different embodiment) Fig 4 of Kawasaki discloses said first surface of said substrate has a functional section (Central portion; Fig 4), said first and second chips (1/2; Fig 2; ¶ [0039]) being located within said functional section (Central portion; Fig 4), and
wherein said light-emitting device further comprises a first metal layer (3; Fig 4) that is disposed on said functional section of said first surface and between said first and second chips and said first surface of said substrate, said first metal layer being formed with a spacing to form two electrical isolation areas (20; Fig 4).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a first metal layer is disposed on said functional sectional in order to form the device with desired design with electrodes being disposed in different configurations (FIG 3).
Regarding claim 12, Fig 4 of Kawasaki discloses said first surface of said substrate has a non-functional section (Corner portions; Fig 4) that surrounds said functional section, wherein said light emitting device further comprises a second metal layer (4; Fig 4) that is disposed on said non-functional section of said first surface of said substrate.
Regarding claim 14, Fig 2 of Kawasaki discloses A light-emitting device, comprising:
a substrate (10; Fig 2; ¶ [0039]) including a first surface (Top surface; Fig 2) and a second surface (Bottom surface; Fig 2) opposite to said first surface, said first surface defining a vertical direction perpendicular thereto;
a first chip (1; Fig 2; ¶ [0039]) disposed on said first surface of said substrate (10; Fig 2; ¶ [0039]);
a second chip (2; Fig 2; ¶ [0041]) disposed on said first surface (Top surface; Fig 2) of said substrate (10; Fig 2; ¶ [0039]), and formed with a top surface (Fig 2), a bottom surface (Fig 2) opposite to said top surface, and a plurality of side surfaces that are connected to said top surface and said bottom surface;
a first buffer layer (5/5a; Fig 2; ¶ [0038]) disposed on said top surface (Top surface; Fig 2) of said second chip so as to relieve stress (Since the layer 5/5a comprises the same material as disclosed by the applicant; therefore, buffer layer (5/5a) will disclose the limitation); and
an encapsulating layer (8; Fig 2; ¶ [0051]) made of silicone-containing resin (¶ [0051]) and disposed on said first surface (Top surface; Fig 2) of said substrate to allow said first chip (1; Fig 2; ¶ [0039]), said first buffer layer (5/5a; Fig 2; ¶ [0038]) and said second chip (2; Fig 2; ¶ [0041]) to be encapsulated between said substrate (10; Fig 2; ¶ [0039]) and said encapsulating layer (8; Fig 2; ¶ [0051]),
wherein each of said first chip and said second chip has a thickness in said vertical direction and said thickness of said first chip is greater than that of said second chip (Fig 2),
wherein said encapsulating layer (8; Fig 2; ¶ [0051]) is in contact with at least a portion of said first surface (Top surface; Fig 1) of said substrate (10; Fig 2; ¶ [0039]) and a surface of said first buffer layer (5/5a; Fig 2; ¶ [0038]) opposite to said second chip, such that said first buffer layer (5/5a; Fig 2; ¶ [0038]) connects said second chip (2; Fig 2; ¶ [0041]) to said encapsulating layer (8; Fig 2; ¶ [0051]).
However Kawasaki does not expressly disclose the following:
a first chip including a first type semiconductor layer, a second type semiconductor layer, and an active layer that is interposed between said first type semiconductor layer and said second type semiconductor layer and that is configured to emit a light;
an encapsulating layer made of fluorine-containing resin.
In the same field of endeavor, Fig 1 of Ota discloses an encapsulating layer can be made up of silicone containing resin or fluorine containing resin (¶ [0059]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that an encapsulating layer is made up of fluorine containing resin or silicone containing resin for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06).
However Kawasaki in view of Ota does not expressly disclose the following:
a first chip including a first type semiconductor layer, a second type semiconductor layer, and an active layer that is interposed between said first type semiconductor layer and said second type semiconductor layer and that is configured to emit a light.
In the same field of endeavor, Kawasaki discloses a first chip (10; Fig 3; ¶ [0057]) disposed on a first surface (Top surface; Fig 3) of said substrate and including a first type semiconductor layer (¶ [0036]), a second type semiconductor layer (¶ [0036]) and an active layer (¶ [0036]) that is interposed between said first type semiconductor layer and said second type semiconductor layer and that is configured to emit a light (¶ [0036]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a first chip disposed on the substrate includes a first type semiconductor layer, a second type semiconductor layer, and an active layer that is interposed between said first type semiconductor layer and said second type semiconductor layer in order for the light emitting chip to emit light (¶ [0036]).
Regarding claim 15, Fig 2 of Kawasaki discloses said first buffer layer (5/5a; Fig 2; ¶ [0038]) further covers said side surfaces (Fig 2) of said second chip (2; Fig 2; ¶ [0041]).
Regarding claim 18, Fig 2 of Kawasaki discloses said first surface extends along a first direction and a second direction intersecting said first direction, the first direction and the second direction being perpendicular to the vertical direction (Fig 2),
wherein said substrate (10; Fig 2; ¶ [0039]) has a first edge and a second edge spaced apart from each other in one of said first direction and said second direction, said first chip being disposed adjacent to said first edge and said second chip being disposed adjacent to said second edge and
wherein said first chip is distant from said second edge by a second minimum distance and said first minimum distance being greater than said second minimum distance. (Fig 2).
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki et al (US 2010/0133571; hereinafter Kawasaki) in view of Ota et al (US 2016/0233396; hereinafter Ota) and Yamamoto et al (US 2020/0343422; hereinafter Yamamoto) as applied to claim 1 and further in view of Hashimoto (US 2016/0172265; hereinafter Hashimoto).
Regarding claim 3, Kawasaki does not expressly disclose said thickness of said first buffer layer comprising epoxy resin (¶ [0054]) ranges from 10 µm to 200 µm.
In the same field of endeavor, Hashimoto discloses thickness of buffer layer comprising epoxy resin can have a thickness of 20 µm which anticipates the claimed range (¶ [0049]).
Accordingly it would have been to the person in the ordinary skill in the art before the effective filing date of the invention such that thickness of buffer layer comprising epoxy resin is within the claimed range for the purpose of forming a buffer having an elastic modulus lower than that of support substrate (¶ [0049]).
Regarding claim 4, Kawasaki does not expressly disclose said thickness of said first buffer layer comprising epoxy resin (¶ [0054]) ranges from 10 µm to 50 µm.
In the same field of endeavor, Hashimoto discloses thickness of buffer layer comprising epoxy resin can have a thickness of 20 µm which anticipates the claimed range (¶ [0049]).
Accordingly it would have been to the person in the ordinary skill in the art before the effective filing date of the invention such that thickness of buffer layer comprising epoxy resin is within the claimed range for the purpose of forming a buffer having an elastic modulus lower than that of support substrate (¶ [0049]).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki et al (US 2010/0133571; hereinafter Kawasaki) in view of Ota et al (US 2016/0233396; hereinafter Ota) and Yamamoto et al (US 2020/0343422; hereinafter Yamamoto) as applied to claim 1 and further in view of Shigtani et al (US 2022/0120948; hereinafter Shigtani).
Regarding claim 6, Fig 2 of Kawasaki discloses said first chip (1; Fig 2) is a blue LED (¶ [0036]).
However Kawasaki does not expressly disclose said first chip emits the light having a wavelength which falls within a range of 200 nm to 380 nm or range of 780 nm to 1000 nm.
In the same field of endeavor, Shigitani discloses a blue LED element has a main light emission peak in a wavelength range of 380 nm (¶ [0114]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that first chip emits light having a wavelength within the claimed range for the purpose of using the well known wavelength range known in the art for blue light emitting chip (¶ [0114]).
Claim(s) 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki et al (US 2010/0133571; hereinafter Kawasaki) in view of Ota et al (US 2016/0233396; hereinafter Ota) and Yamamoto et al (US 2020/0343422; hereinafter Yamamoto) as applied to claim 14 and further in view of Naka et al (US 2016/0204321; hereinafter Naka).
Regarding claim 16, Kawasaki discloses said thickness of said first chip (1; Fig 2) is greater (Fig 2) than that of second chip (2; Fig 2).
However Kawasaki does not expressly disclose thickness of said first chip is greater than that of said second chip by not less than 50 µm.
In the same field of endeavor, Naka discloses a thickness of light emitting chip is 200 µm (¶ [0048]) and a thickness of a second chip (Zener diode) is 85 µm.
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that light emitting chip and second chip is formed of certain thickness in order to form a structure that helps in improving light extraction efficiency.
Therefore Kawasaki in view of Naka disclose the limitation thickness of said first chip is greater than that of second chip by not less than 50 µm.
Regarding claim 17, Kawasaki discloses said thickness of said first chip (1; Fig 2) is greater (Fig 2) than that of second chip (2; Fig 2).
However Kawasaki does not expressly disclose thickness of said first chip is greater than that of said second chip by not less than 50 µm to 300 µm.
In the same field of endeavor, Naka discloses a thickness of light emitting chip is 200 µm (¶ [0048]) and a thickness of a second chip (Zener diode) is 85 µm.
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that light emitting chip and second chip is formed of certain thickness in order to form a structure that helps in improving light extraction efficiency.
Therefore Kawasaki in view of Naka disclose the limitation thickness of said first chip is greater than that of second chip by not less than 50 µm to 300 µm.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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