DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/20/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Species A and sub-species C in the reply filed on 1/16/2026 is acknowledged. The traversal is on the ground(s) that there is no undue burden on the examiner to consider all the claims in the single application. This is not found persuasive because the species or groupings of patentably indistinct species require a different field of search (e.g., searching different classes /subclasses or electronic resources, or employing different search strategies or search queries).
The requirement is still deemed proper and is therefore made FINAL.
Claims 7-8, 11, 13 and 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species and sub-species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1/16/2026.
Claim Objections
Claim 14 is objected to because of the following informalities: “a first chip disposed on said first surface of said packaging substrate” should be “a first chip disposed on said first surface of said substrate”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 9, 14-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al (US 2020/0343422; hereinafter Yamamoto) in further view of Kurihara (US 2023/0246042; hereinafter Kurihara).
Regarding claim 1, Figs 3 and 4H of Yamamoto discloses a light-emitting device comprising:
a substrate (5; Fig 3; ¶ [0032]) including a first surface (Top surface; Fig 3) and a second surface (Bottom surface; Fig 3) opposite to said first surface, said first surface extending along a first direction (Horizontal Direction; Fig 3) and a second direction (Vertical Direction; Fig 3) intersecting the first direction;
a first chip (10; Fig 3; ¶ [0057]) disposed on said first surface (Top surface; Fig 3) of said substrate (5; Fig 3; ¶ [0032]), and including a first type semiconductor layer (¶ [0036]), a second type semiconductor layer (¶ [0036]), and an active layer (¶ [0036]) that is interposed between said first type semiconductor layer and said second type semiconductor layer and that is configured to emit a light (¶ [0036]);
a second chip (20; Fig 3; ¶ [0032]) disposed on said first surface (Top surface; Fig 3) of said substrate, and formed with a top surface, a bottom surface opposite to said top surface, and a plurality of side surfaces (Side surface of chip 20; Fig 3) that are connected to said top surface and said bottom surface; a first buffer layer (40; Figs 3 and 4H; ¶ [0032]) disposed on said top surface of said second chip so as to relieve stress (Since the layer 40 comprises the same material as disclosed by the applicant; therefore buffer layer (40) will disclose the limitation); and
an encapsulating layer (30; Fig 3; ¶ [0035]) comprising lens made of resin (¶ [0053]) and disposed on said first surface of said substrate to allow said first chip (10; Fig 3; ¶ [0057]), said first buffer layer (40; Figs 3 and 4H; ¶ [0032]) and said second chip (20; Fig 3; ¶ [0032]) to be encapsulated between said substrate (5; Fig 3; ¶ [0032]) and said encapsulating layer (30; Fig 3; ¶ [0035]),
wherein said substrate (5; Fig 3; ¶ [0032]) has two edges (Two side edges; Fig 3) spaced apart from each other in one of said first direction and said second direction, said first chip (10; Fig 3; ¶ [0057]) having a first minimum distance (Distance from left edge to first chip; Fig 3) distant from one (Left Edge; Fig 3) of said two edges in one of said first direction (Horizontal Direction; Fig 3) and said second direction (Vertical Direction; Fig 3), said second chip (20; Fig 3; ¶ [0032]) having a second minimum distance (Distance from the left edge to second chip; Fig 3) distant from one of said two edges (Two side edges; Fig 3) in a corresponding one of said first direction and said second direction, said first minimum distance (Distance from the left edge to second chip; Fig 3) being greater than said second minimum distance (Distance from the left edge to second chip; Fig 3).
However Yamamoto does not expressly disclose an encapsulating layer made of fluorine-containing resin.
In the same field of endeavor, Kurihara discloses a lens can be made of fluorine-based resin (¶ [0062]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that an encapsulating layer comprising a lens can be made of fluorine comprising resin as it is well-known and suitable insulating material known in the art for forming a on-chip lens (¶ [0062]).
Regarding claim 2, Figs 3 and 4H of Yamamoto discloses said first buffer layer (40; Figs 3 and 4H; ¶ [0032]) further covers said side surfaces of said second chip (Fig 4H).
Regarding claim 5, Figs 3 and 4H of Yamamoto discloses said first buffer layer (40; Figs 3 and 4H; ¶ [0032]) is made of epoxy resin (¶ [0047]).
Regarding claim 9, Figs 3 and 4H of Yamamoto discloses said second chip (20; Fig 3; ¶ [0032]) is an electrostatic discharge protection chip (¶ [0057]).
Regarding claim 14, Figs 3 and 4H of Yamamoto discloses a light-emitting device comprising:
a substrate (5; Fig 3; ¶ [0032]) including a first surface (Top surface; Fig 3) and a second surface (Bottom surface; Fig 3) opposite to said first surface, said first surface defining a vertical direction perpendicular thereof;
a first chip (10; Fig 3; ¶ [0057]) disposed on said first surface (Top surface; Fig 3) of said substrate (5; Fig 3; ¶ [0032]), and including a first type semiconductor layer (¶ [0036]), a second type semiconductor layer (¶ [0036]), and an active layer (¶ [0036]) that is interposed between said first type semiconductor layer and said second type semiconductor layer and that is configured to emit a light (¶ [0036]);
a second chip (20; Fig 3; ¶ [0032]) disposed on said first surface (Top surface; Fig 3) of said substrate, and formed with a top surface, a bottom surface opposite to said top surface, and a plurality of side surfaces (Side surface of chip 20; Fig 3) that are connected to said top surface and said bottom surface;
a first buffer layer (40; Figs 3 and 4H; ¶ [0032]) disposed on said top surface of said second chip so as to relieve stress (Since the layer 40 comprises the same material as disclosed by the applicant; therefore buffer layer (40) will disclose the limitation); and
an encapsulating layer (30; Fig 3; ¶ [0035]) comprising lens made of resin (¶ [0053]) and disposed on said first surface of said substrate to allow said first chip (10; Fig 3; ¶ [0057]), said first buffer layer (40; Figs 3 and 4H; ¶ [0032]) and said second chip (20; Fig 3; ¶ [0032]) to be encapsulated between said substrate (5; Fig 3; ¶ [0032]) and said encapsulating layer (30; Fig 3; ¶ [0035]),
wherein each of said first chip and second chip has a thickness in said vertical direction and said thickness of said first chip is greater than that of said second chip (Fig 3)
However Yamamoto does not expressly disclose an encapsulating layer made of fluorine-containing resin.
In the same field of endeavor, Kurihara discloses a lens can be made of fluorine-based resin (¶ [0062]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that an encapsulating layer comprising a lens can be made of fluorine comprising resin as it is well-known and suitable insulating material known in the art for forming a on-chip lens (¶ [0062]).
Regarding claim 15, Figs 3 and 4H of Yamamoto discloses said first buffer layer (40; Figs 3 and 4H; ¶ [0032]) further covers said side surfaces of said second chip (Fig 4H).
Regarding claim 18, Figs 3 and 4H of Yamamoto discloses said first surface extends along a first direction (Fig 3) and a second direction (Fig 3) intersecting said first direction, both the first and second directions being perpendicular to the vertical direction (Fig 3), and
wherein said substrate has first (Left edge; Fig 3) and second edges (Right edge; fig 3) spaced apart from each other in one of said first direction and said second direction, said first chip (10; Fig 3; ¶ [0057]) disposed adjacent to said first edge, and said second chip (20; Fig 3; ¶ [0057]) disposed adjacent to said second edge,
wherein said first chip is distant from said first edge (Left Edge; Fig 3) by a first minimum distance (Distance from left edge to first chip; Fig 3), said second chip being distant from said second edge (20; Fig 3; ¶ [0032]) by a second minimum distance, and said first minimum distance being greater (Fig 3) than said second minimum distance.
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al (US 2020/0343422; hereinafter Yamamoto) in view of Kurihara (US 2023/0246042; hereinafter Kurihara) and further in view of Hashimoto (US 2016/0172265; hereinafter Hashimoto).
Regarding claim 3, Yamamoto does not expressly disclose said thickness of said first buffer layer comprising epoxy resin ranges from 10 µm to 200 µm.
In the same field of endeavor, Hashimoto discloses thickness of buffer layer comprising epoxy resin can have thickness of 20 µm which anticipates the claimed range (¶ [0049]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that thickness of buffer layer comprising epoxy resin is within the claimed range for the purpose of forming a buffer having an elastic modulus lower than that of support substrate (¶ [0049]).
Regarding claim 4, Yamamoto does not expressly disclose said thickness of said first buffer layer comprising epoxy resin ranges from 10 µm to 50 µm.
In the same field of endeavor, Hashimoto discloses thickness of buffer layer comprising epoxy resin can have thickness of 20 µm which anticipates the claimed range (¶ [0049]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that thickness of buffer layer comprising epoxy resin is within the claimed range for the purpose of forming a buffer having an elastic modulus lower than that of support substrate (¶ [0049]).
Claim(s) 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al (US 2020/0343422; hereinafter Yamamoto) in view of Kurihara (US 2023/0246042; hereinafter Kurihara) and further in view of Ono (US 2011/0012151; hereinafter Ono).
Regarding claim 10, Yamamoto in view of Kurihara said first surface of said substrate has a functional section, said first and second chips being located within said functional section, and
wherein said light-emitting device further comprises a first metal layer that is disposed on said functional section of said first surface and between said first and second chips and said first surface of said substrate, said first metal layer being formed with a spacing to form two electrical isolation areas.
In the same field of endeavor, Fig 2C of Ono discloses first surface (Top surface; Fig 2C) of a substrate (24; Fig 2C; ¶ [0020]) has a functional section (Center Portion; Fig 2C), first and second chips (10a/10b; Fig 2C; ¶ [0018]) are being located within said functional section, and
wherein said light-emitting device further comprises a first metal layer (130c; Fig 3B; ¶ [0037]) that is disposed on said functional section of said first surface and between said first and second chips and said first surface of said substrate, said first metal layer being formed with a spacing to form two electrical isolation areas. (Fig 3B)
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a first metal layer that is disposed on said functional section of said first surface and between said first and second chips and said first surface of said substrate, said first metal layer being formed with a spacing to form two electrical isolation areas in order to form the conductive portions that serve as wire bonding regions (¶ [0037]).
Regarding claim 12, Yamamoto in view of Ono as modified above in claim 10 (Fig 3B of Ono in particular) discloses said first surface of said substrate has a non-functional section (Corner portions; Fig 3B) that surrounds said functional section,
Wherein said light-emitting device further comprises a second metal layer (130d; Fig 3B; ¶ [0037]) that is disposed on said non-functional section of said first surface of said substrate. (Fig 3B)
Claim(s) 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al (US 2020/0343422; hereinafter Yamamoto) in view of Kurihara (US 2023/0246042; hereinafter Kurihara) and further in view of Naka et al (US 2016/0204321; hereinafter Naka).
Regarding claim 16, Yamamoto discloses said thickness of said first chip (10; Fig 3; ¶ [0057]) is greater (Fig 3) than that of second chip (20; Fig 3; ¶ [0057]).
However Yamamoto does not expressly disclose thickness of said first chip is greater than that of said second chip by not less than 50 µm.
In the same field of endeavor, Naka discloses a thickness of light emitting chip is 200 µm (¶ [0048]) and a thickness of a second chip (Zener diode) is 85 µm.
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that light emitting chip and second chip is formed of certain thickness in order to form a structure that helps in improving light extraction efficiency.
Therefore Yamamoto in view of Naka will disclose the limitation thickness of said first chip is greater than that of said second chip by not less than 50 µm.
Regarding claim 17, Yamamoto discloses said thickness of said first chip (10; Fig 3; ¶ [0057]) is greater (Fig 3) than that of second chip (20; Fig 3; ¶ [0057]).
However Yamamoto does not expressly disclose thickness of said first chip is greater than that of said second chip by not less than 50 µm to 300 µm.
In the same field of endeavor, Naka discloses a thickness of light emitting chip is 200 µm (¶ [0048]) and a thickness of a second chip (Zener diode) is 85 µm.
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that light emitting chip and second chip is formed of certain thickness in order to form a structure that helps in improving light extraction efficiency.
Therefore Yamamoto in view of Naka will disclose the limitation thickness of said first chip is greater than that of said second chip by not less than 50 µm to 300 µm.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al (US 2020/0343422; hereinafter Yamamoto) in view of Kurihara (US 2023/0246042; hereinafter Kurihara) and further in view of Ting et al (US 2020/0126475; hereinafter Ting).
Regarding claim 6, Yamamoto discloses said first chips emits the ultraviolet light (¶ [0036]).
However Yamamoto does not expressly disclose said first chip emits the light having a wavelength which falls within a range of 200 nm to 380 nm or a range of 780 nm to 1000 nm.
In the same field of endeavor, Ting discloses a light emitting chip emitting ultraviolet light having a wavelength of 300 nm (¶ [0056]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a light emitting chip emitting ultraviolet light having a wavelength within the claimed range for the purpose of using well known and suitable wavelength known in the art for ultraviolet light. (¶ [0056]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hussell (US 2019/0371974; This prior art discloses Light Emitting Diode Display Device comprising light-transmissive layer such that light emitted from one or more LED can pass through the wavelength-conversion material)
Toita et al (US 2018/0219124; This prior art discloses light emitting diode display with a second chip comprising Zener diode that acts an electrostatic discharge protection device)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817