DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election without traverse of Species C, identified as encompassing claims 1-20 is acknowledged.
Note by the Examiner
3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-2, 6, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0122977 A1), hereinafter as K1, in view of Tauchi et al. (US 2018/0211778 A1), hereinafter as T1
[Chia (US 2022/0328696 A1), hereinafter as C1, and Sharma et al. (US 2023/0276624 A1), hereinafter as S1 are utilized herein as evidence]
5. Regarding Claim 1, K1 discloses a semiconductor device (see in particular Figs. 18A-B and [0013] “semiconductor device”) comprising:
a plurality of bit lines (elements 26, see [0046] “bit lines 26”) arranged on a substrate (element 11, see [0042] “substrate 11”) and extending in a first horizontal direction (see Figs. 18A-B first horizontal D3 direction);
a plurality of channel layers (elements 22M, see [0055] “active layers 22M”) respectively arranged on the plurality of bit lines (see Fig. 18B);
a plurality of word lines (elements 32, see [0053] “word line 32”) respectively arranged on the plurality of channel layers (see Figs. 18A-B), and extending in a second horizontal direction (second horizontal direction D1); and
a plurality of ferroelectric layers (ferroelectric layers among the gate dielectric layers elements 31, see [0027] “gate dielectric layer GD may include, for example, silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an anti-ferroelectric, or a combination thereof” and [0052] “gate dielectric layers 31” Selected as a multilayer having at least a ferroelectric material and a dielectric material) arranged between the plurality of channel layers and the plurality of word lines (see Figs. 18A-B),
wherein the plurality of ferroelectric layers comprise a base dielectric layer (see [0027] the ferroelectric layer is part of the gate dielectric layer which is a dielectric).
K1 does not disclose a nanoparticle, the nanoparticle dispersed and arranged in the base dielectric layer, respectively, wherein the nanoparticle has a core-shell structure including a core and a shell, wherein the core includes a portion formed inside the nanoparticle and having a particular volume, and wherein the shell includes a portion corresponding to the nanoparticle except for the core and at least partially surrounds the core.
T1 discloses (see Figs. 2-3) a base dielectric layer (element 300 excluding elements 30, see [0036] “dielectric composition 300 according to this embodiment comprises single-phase particles 20 which do not have a core-shell structure, and core-shell particles 30 which have a core-shell structure”) and a nanoparticle (elements 30, see [0036] “core-shell particles 30”), the nanoparticle dispersed and arranged in the base dielectric layer (see Figs. 2-3), respectively, wherein the nanoparticle has a core-shell structure including a core and a shell (see [0036]), wherein the core includes a portion formed inside the nanoparticle and having a particular volume (see Figs. 2-3 and [0039-0040]), and wherein the shell includes a portion corresponding to the nanoparticle except for the core and at least partially surrounds the core (see Figs. 2-3 and [0039-0040]).
The nanoparticles as taught by T1 are incorporated as nanoparticles of K1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of T1 with K1 because the combination allows for improved temperature characteristics of dielectric constant (see T1 [0004]); and the combination is use of a known technique to improve similar devices (methods, or products) in the same way (see evidentiary reference C1 [0016] “embedding, for example, aluminum nanoclusters within the ferroelectric material increases a switching performance of the ferroelectric memory cell, thereby increasing uniformity of the program and erase voltages across the memory array. This is because the aluminum nanoclusters may assist in nucleation of the ferroelectric domains under the presence of the program voltage or erase voltage, thereby increasing a switching speed of the ferroelectric domains across the ferroelectric structures” and see evidentiary reference S1 [0056] “memory material 118 comprises conductive nanoparticles (e.g., ruthenium nanoparticles, crystalline nanoparticles, metal dots) embedded within an insulative material (e.g., hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx))”).
6. Regarding Claim 2, K1, T1 disclose the semiconductor device of claim 1, wherein the core and the nanoparticle each has a substantially spherical shape (see T1 Fig. 3 and [0045-0046, 0060] The cross-section shows the shape of the core and the nanoparticle each has a substantially spherical shape and have a starting powder material particle size of 0.1 μm - 1 μm meaning the three dimensional structure is substantially spherical).
7. Regarding Claim 6, K1, T1 disclose the semiconductor device of claim 1, further comprising (see K1) a gate insulating layer (dielectric layer among the gate dielectric layers elements 31, see [0027] “gate dielectric layer GD may include, for example, silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an anti-ferroelectric, or a combination thereof” and [0052] “gate dielectric layers 31” Selected as a multilayer having at least a ferroelectric material and a dielectric material) arranged between the ferroelectric layer and the channel layer (see [0027] Selected in the combination to have the gate insulating layer between the ferroelectric layer and the channel layer).
8. Regarding Claim 12, K1, T1 disclose the semiconductor device of claim 1,
wherein the channel layer comprises at least one of polysilicon (see K1 [0042] “semiconductor layers 22 may include, for example, a polysilicon layer”), silicon-germanium, InGaZnOx (IGZO), Sn-doped IGZO, W-doped InOx (IWO), CuS2, CuSe2, WSe2, InZnOx (IZO), ZnSnOx (ZTO), YZnOx (YZO), MoS2, MoSe2, and WS2.
9. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0122977 A1), hereinafter as K1, in view of Tauchi et al. (US 2018/0211778 A1), hereinafter as T1, in view of Rajashekhar et al. (US 2021/0242241 A1), hereinafter as R1
10. Regarding Claim 10, K1, T1 disclose the semiconductor device of claim 1, wherein the base dielectric layer comprises a ferroelectric material (see K1 [0027] “gate dielectric layer GD may include, for example, silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an anti-ferroelectric, or a combination thereof”).
K1, T1 do not disclose wherein the base dielectric layer comprises a ferroelectric material having a chemical formula of HfxM1-xOy (0 < x < 1, 2 < y ≤ 4, and M includes at least one of Zr, Si, Al, Y, Gd, La, Sc, and Sr), and the ferroelectric material has an orthorhombic crystal structure.
R1 discloses the ferroelectric material having a chemical formula of HfxM1-xOy (0 < x < 1, 2 < y ≤ 4, and M includes at least one of Zr, Si, Al, Y, Gd, La, Sc, and Sr), and the ferroelectric material has an orthorhombic crystal structure (see [0162] “the memory material layer 154L may include the ferroelectric non-centrosymmetric orthorhombic phase of doped or undoped hafnium oxide layer … the memory material layer 154L may consist essentially of HfxZr1-xO2, in which x is in a range between 0.1 to 0.6, such as 0.2 to 0.5”).
The specific ferroelectric material as taught by R1 is incorporated as the specific ferroelectric material of K1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of R1 with K1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known ferroelectric material for another in a similar device to obtain predictable results (see R1 [0162]).
Allowable Subject Matter
11. Claims 13-20 are allowed
Claims 3-5, 7-9, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
12. Claim 3, “the shell comprises a metal oxide having a greater bandgap energy than a material constituting the base dielectric layer.” – as instantly claimed and in combination with the additionally claimed limitations.
13. Claim 4, “the shell comprises aluminum oxide” – as instantly claimed and in combination with the additionally claimed limitations.
14. Claim 5, “the core comprises tungsten (W) or silicon oxide (SiO2)” – as instantly claimed and in combination with the additionally claimed limitations.
15. Claim 7, “a mold insulating layer including a plurality of openings respectively arranged on the plurality of bit lines, and one or more of the plurality of openings extending in the second horizontal direction, wherein a channel layer of the plurality of channel layers comprises: a first vertical extension portion arranged on a first sidewall of an opening of the plurality of the openings; a second vertical extension portion arranged on a second sidewall of the opening; and a horizontal extension portion arranged on a bottom portion of the opening and arranged on a respective bit line of the plurality of bit lines” – as instantly claimed and in combination with the additionally claimed limitations.
16. Claim 8, “a mold insulating layer including a plurality of openings respectively arranged on the plurality of bit lines, and one or more of the plurality of openings extending in the second horizontal direction, wherein a word line of the plurality of word lines comprises a first word line arranged on a first sidewall of an opening of each mold insulating layer, with the channel layer and the ferroelectric layer arranged therebetween, and wherein a second word line arranged on a second sidewall of the opening of the mold insulating layer, with the channel layer and the ferroelectric layer arranged therebetween” – as instantly claimed and in combination with the additionally claimed limitations.
17. Claim 9, “spacers arranged on the plurality of word lines, wherein one or more of the plurality of word lines have a vertical cross-section of L shape” – as instantly claimed and in combination with the additionally claimed limitations.
18. Claim 11, “a thickness of the ferroelectric material exceeds 0 nm and is equal to or less than about 10 nm, and a diameter of the nano particle exceeds 0 nm and equal to or less than about two thirds of the thickness of the ferroelectric material” – as instantly claimed and in combination with the additionally claimed limitations.
19. Claim 13, “a plurality of mold insulating layers respectively arranged on the plurality of bit lines, one or more of the plurality of mold insulating layers including a plurality of openings extending in a second horizontal direction substantially vertical to the first horizontal direction; a first cell transistor arranged on a first sidewall of an opening of the plurality of openings; and a second cell transistor arranged on a second sidewall of the opening, wherein the first cell transistor comprises: a first channel layer arranged on the first sidewall of the opening; a first ferroelectric material arranged on the first channel layer; and a first word line arranged on the first ferroelectric material and extending in the second horizontal direction, wherein the second cell transistor comprises: a second channel layer arranged on the second sidewall of the opening; a second ferroelectric material arranged on the second channel layer; and a second word line arranged on the second ferroelectric material and extending in the second horizontal direction, wherein the first ferroelectric material and the second ferroelectric material each comprises a base dielectric layer and nanoparticles, the nanoparticles having a core-shell structure including a core and a shell and the nanoparticles distributed and arranged in the base dielectric layer, wherein the core comprises a center of the nano particle, and wherein the shell comprises a portion except for the core in the nano particle and at least partially surrounds the core” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on the current claim incorporate the same allowable subject matter.
20. Claim 18, “a channel layer including a first vertical extension portion arranged on the bit line and extending in a vertical direction substantially vertical to an upper surface of the substrate, a second vertical extension portion spaced apart from the first vertical extension portion and extending in the vertical direction, and a horizontal extension portion connected to bottom portions of the first vertical extension portion and the second vertical extension portion and extending in the first horizontal direction; a gate insulating layer arranged on the first vertical extension portion and the second vertical extension portion; a ferroelectric layer arranged on the gate insulating layer; and a plurality of word lines arranged on the ferroelectric layer and extending in a second horizontal direction substantially vertical to the first horizontal direction, the plurality of word lines including first word lines arranged on the first vertical extension portion with the gate insulating layer and the ferroelectric layer arranged therebetween and second word lines arranged on the second vertical extension portion with the gate insulating layer and the ferroelectric layer arranged therebetween, wherein the ferroelectric layer comprises a base dielectric layer and a nanoparticle, the nanoparticle dispersed and arranged in the base dielectric layer, the nanoparticle has a core-shell structure, the nanoparticle and the core have a spherical shape having a substantially concentric cross-section, and the shell includes a portion corresponding to the nanoparticle except for the core and at least partially surrounds the core” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on the current claim incorporate the same allowable subject matter.
Conclusion
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/SAMUEL PARK/Examiner, Art Unit 2818