DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species A, Claims 1-9 in the reply filed on November 21, 2025 is acknowledged.
Claims 10-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species and/or a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on November 21, 2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) submitted on March 21, 2023 and August 22, 2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0062392 A1 (hereinafter “Cheng”).
Regarding claim 1, Cheng discloses a manufacturing method of an electronic device (300; [0008] and [0031]), comprising:
providing a substrate (202; Fig. 2A; [0015]);
forming a conductive layer (238; Fig. 2A; [0018]) on the substrate;
forming a circuit structure (102, 104, 112, 120, 126, 130, 132; Fig. 2C; [0009]-[0013] and [0020]) on the conductive layer; and
patterning the circuit structure to form at least one opening (150; Figs. 2B, 2D, 2G; [0019], [0021] and [0024]),
wherein the at least one opening has a stepped profile (Fig. 2H; [0025]).
Regarding claim 2, Cheng discloses forming the circuit structure on the conductive layer comprises:
forming a dielectric layer (126, 130, 132; Fig. 2C; [0009], [0012]-[0013] and [0020]) on the conductive layer;
patterning the dielectric layer to form a first sub-opening (134; Fig. 2B; [0019]);
forming an active component layer (102, 104, 112, 120; Fig. 2C; [0009]-[0011]) on the dielectric layer; and
patterning the active component layer to form a second sub-opening (136; Figs. 2D, 2G; [0021] and [0024]),
wherein the second sub-opening corresponds to the first sub-opening in a top view direction of the substrate to define the at least one opening (Fig. 2G; [0024]).
Regarding claim 3, Cheng discloses the dielectric layer comprises a multi-layer structure (126, 130, 132; [0009] and [0012]-[0013]).
Regarding claim 4, Cheng discloses an etching process is performed to form the first sub-opening and the second sub-opening, and the etching process comprises a wet etching process, a dry etching process, or a combination thereof ([0019], [0021] and [0024]).
Regarding claim 9, Cheng discloses in forming the circuit structure on the conductive layer, an active component (104; Fig. 2C; [0011]) is formed, and the active component is electrically connected to a chip (100; Fig. 2C; [0010]).
Claim(s) 1, 6 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0343179 A1 (hereinafter “Kuo”).
Regarding claim 1, Kuo discloses a manufacturing method of an electronic device, comprising:
providing a substrate (C; Fig. 1A; [0013]);
forming a conductive layer (104d; Fig. 1A; [0014]) on the substrate;
forming a circuit structure (110, 116; Figs. 1B-1C; [0016]-[0018]) on the conductive layer; and
patterning the circuit structure to form at least one opening (148; Figs. 5A-5B; [0036]-[0037]),
wherein the at least one opening has a stepped profile (Fig. 5B).
Regarding claim 6, Kuo discloses forming a bonding pad (154; Fig. 5C; [0038]) in the at least one opening.
Regarding claim 8, Kuo discloses providing a chip (126; Fig. 5C; [0038]) on the bonding pad, wherein the chip is electrically connected to the conductive layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of US 2010/0319974 A1 (hereinafter “Ishizuka”).
Regarding claim 5, Cheng discloses the manufacturing method of the electronic device according to claim 2.
Cheng does not disclose there is an interval between the second sub-opening and the first sub-opening in a first direction and a second direction, the first direction is orthogonal to the second direction, the first direction and the second direction are orthogonal to the top view direction of the substrate, and the interval is greater than or equal to 5 [Symbol font/0x6D]m.
Ishizuka teaches in Figs. 1, 2 and related text there is an interval between the second sub-opening (7b; [0051]) and the first sub-opening (7a; [0051]) in a first direction (the horizontal direction in the top view of Fig. 2) and a second direction (the vertical direction in the top view of Fig. 2), the first direction is orthogonal to the second direction, the first direction and the second direction are orthogonal to the top view direction of the substrate.
Ishizuka does not explicitly teach the interval is greater than or equal to 5 [Symbol font/0x6D]m. However, Ishizuka states in [0031]: “According to the present invention, the connecting opening section(s) can be easily changed to have a suitable mode (shape, size, and the like) for an electronic element or an external terminal(s) of the electronic element, depending on a mode (shape, size, and the like) of the electronic element or the external terminal(s) thereof.” Ishizuka further states in [0091]: “According to the present invention, modes (size, shape, position, number, and the like) of the connecting opening section(s) (the first and second opening sections and step section(s)) can be changed depending on the type (shape or size) of an electronic element mounted on the printed wiring board or the type (shape or size) of the external terminal(s) of the electronic element.”
Cheng and Ishizuka are analogous art because they both are directed to electronic devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng with the specified features of Ishizuka because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form an interval between the second sub-opening and the first sub-opening in a first direction and a second direction, wherein the first direction is orthogonal to the second direction, wherein the first direction and the second direction are orthogonal to the top view direction of the substrate, as taught by Ishizuka, and wherein the interval is greater than or equal to 5 [Symbol font/0x6D]m, in order to improve filling of the first sub-opening and the second sub-opening (e.g., to reduce the risk of “pinch off” which results in void formation), and in order to accommodate an electronic element or an external terminal having a micrometer-scale size according to the intended use of the electronic device (Ishizuka: [0031] and [0091]).
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1980). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo in view of US 6,645,852 B1 (hereinafter “Taguchi”).
Regarding claim 7, Kuo discloses the manufacturing method of the electronic device according to claim 6, wherein the at least one opening exposes a part of the conductive layer (Fig. 5B; [0037]).
Kuo does not disclose before the bonding pad is formed in the at least one opening, a surface treatment process is performed on a top surface of the exposed conductive layer.
Taguchi teaches in Figs. 1A-1B and related text before the bonding pad (24, 25, 26; col. 4, lines 8-23) is formed in the at least one opening (23; col. 3, lines 47-56), a surface treatment process (col. 3, lines 57-65) is performed on a top surface of the exposed conductive layer (15; col. 3, lines 37-39).
Kuo and Taguchi are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kuo with the specified features of Taguchi because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, before the bonding pad is formed in the at least one opening, to perform a surface treatment process on a top surface of the exposed conductive layer, as taught by Taguchi, in order to enable the top surface of the exposed conductive layer to be cleaned well by a hydrogen plasma treatment, thus making it possible to stably form a copper conductor (e.g., the bonding pad or a wiring) having a low resistivity and a high reliability (Taguchi: col. 2, lines 46-57).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811