DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-9 in the “Reply To The Restriction Requirement Dated October 27, 2025” filed on December 29, 2025 is acknowledged. The traversal is on the grounds that “the Office has failed to demonstrate that a serious search or examination burden would be placed upon the Office if the election was not required.” This is not found persuasive because it is merely a conclusory statement that does not distinctly and specifically point out supposed errors in paragraphs two (2)-eight (8) of the Restriction Requirement dated October 27, 2025 (hereinafter the “Restriction Requirement”), as required by paragraph ten (10) of the Restriction Requirement. The requirement is still deemed proper and is therefore made FINAL.
Newly submitted claims 21-31 are directed to inventions that are independent or distinct from the invention originally claimed in the elected invention of Group I, claims 1-9 for at least the following reasons. For example, the invention of newly added claims 21-27 require “at least one of the third nanostructures having a sidewall contiguous with a sidewall of a dielectric wall” which is a materially different design, mode of operation, function, or effect than the claimed invention of Group I, claims 1-9 which does not include this effect (please see, MPEP §806.05(j) and §802.01). As another example, the invention of newly added claims 28-31 require “at least one of the fourth nanostructures having a sidewall contiguous with a second sidewall of the dielectric wall” which is a materially different design, mode of operation, function, or effect than the claimed invention of Group I, claims 1-9 which does not require this effect. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for at least the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
(a) the inventions have acquired a separate status in the art in view of their different classifications;
(b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries); and/or
(d) the prior art applicable to one invention would not likely be applicable to another invention.
Because Applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, newly added claims 21-31 are withdrawn from consideration as being directed to a non-elected invention. See, 37 CFR §1.142(b) and §1.145, as well as MPEP §821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, Applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should Applicant traverse on the ground that the inventions are not patentably distinct, Applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the Examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on March 21, 2023 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the IDS is being considered by the Examiner.
Claim Objections
Claim 7 is objected to because of the following informalities:
on lines 3-4, “the first quantity of third nanostructures” should be “a third quantity of third nanostructures”;
on lines 7-8, “the second quantity of fourth nanostructures” should be “a fourth quantity of fourth nanostructures”. Appropriate correction is required.
Claim 9 is objected to because of the following informality: on line 1, “The method of claim 8,” should be “The method of claim 7,”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, lines 5-7 recite, “the second transistor comprising a second quantity of second nanostructures, the second quantity being different than the first quantity”. This recited language is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, the meaning of the recitation of the second quantity being different than the first quantity is ambiguous because it is unclear what the difference is between the second quantity of second nanostructures and the first quantity of first nanostructures. Is it a difference in number, height, shape, doping type, doping concentration or something else? For purpose of examination, the Examiner is interpreting lines 5-7 of claim 1 as reciting: “the second transistor comprising a second quantity of second nanostructures, the second quantity being different in number than the first quantity” because of this ambiguity.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0187515 A1 (Yemenicioglu) in view of US 2021/0233909 A1 (Bao).
Regarding claim 1, Yemenicioglu discloses, A method ([0026]) comprising:
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placing a first cell (first cell (102); FIG. 1A; [0036]) in a device layout (device layout (100); FIG. 1A; [0036]), the first cell (102) defining a first transistor (FIGs. 11A-11C; [0120], [0140], and [0143]), the first transistor (FIGs. 11A-11C; [0120], [0140], and [0143]) comprising a first quantity of first nanostructures (first quantity of first nanostructures (110); FIG. 1A; [0036]);
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placing a second cell (second cell (104); FIG. 1A; [0036]) in the device layout (100) directly adjacent to the first cell (102) (FIG. 1A), the second cell (104) defining a second transistor (FIGs. 11A-11C; [0120], [0140], and [0143]), the second transistor (FIGs. 11A-11C; [0120], [0140], and [0143]) comprising a second quantity of second nanostructures (second quantity of second nanostructures (108); FIG. 1A; [0036]);
generating a lithography mask ([0124]) based on the device layout (100); and
manufacturing a semiconductor device (semiconductor device (1100); FIG. 11A; [0141]) using the lithography mask ([0124]).
But, Yemenicioglu does not appear to explicitly disclose, the second quantity being different than the first quantity.1
However, in analogous art, Bao discloses that it is well-known that a semiconductor device (semiconductor device (200) FIG. 2; [0026]) may be predicably fabricated to include a first quantity of first nanostructures (first quantity of first nanostructures (206a); FIG. 2; [0029]), a second quantity of second nanostructures (second quantity of second nanostructures (206b); FIG. 2; [0029]), and a third quantity of third nanostructures (third quantity of third nanostructures (206c); FIG. 2; [0029]).
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Bao also discloses that the number of first quantity of first nanostructures (206a) may be different than the number of second quantity of second nanostructures (206b) and the number of third quantity of third nanostructures (206c); the number of second quantity of second nanostructures (206b) may be different than the number of first quantity of first nanostructures (206a) and the number of third quantity of third nanostructures (206c); and the number of third quantity of third nanostructures (206c) may be different than the number of first quantity of first nanostructures (206a) and the number of second quantity of second nanostructures (206b) ([0035]). Bao additionally discloses that the different numbers of the first quantity of first nanostructures (206a), the second quantity of second nanostructures (206b), and the third quantity of third nanostructures (206c) allows the characteristics of corresponding transistors to be tuned based on the type of transistor device and/or current flow associated with such a transistor device type ([0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yemenicioglu and Bao before him/her, that the second transistor of Yemenicioglu could be predicably fabricated so that the second quantity of second nanostructures of the second transistor is different than the first quantity of first nanostructures of the first transistor of Yemenicioglu, as taught Bao, so that the characteristics of first and second transistors of Yemenicioglu can be tuned based on the device types of the first and second transistors and/or current flow associated with such device types, as also taught by Bao.
Regarding claim 2, Yemenicioglu in view of Bao discloses, The method ([0026]) of claim 1, wherein a first size (first size (114); FIG. 2; [0036]) of the first cell (102) is the same as a second size (second size (114); FIG. 2; [0036]) of the second cell (104).
Regarding claim 4, Yemenicioglu in view of Bao discloses, The method ([0026]) of claim 1, wherein the first transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu) further comprises a first gate structure (first gate structure (110); FIG. 1C; [0022], all of Bao) extending around a third quantity of sides (annotated FIG. 1C of Bao, below) of each of the first nanostructures (first nanostructures (106a); FIG. 1C; [0021], all of Bao), and the second transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu) further comprises a second gate structure (second gate structure (110); FIG. 1C; [0022], all of Bao) extending around the third quantity of sides (annotated FIG. 1C of Bao, below) of each of the second nanostructures (second nanostructures (106b); FIG. 1C; [0021], all of Bao).
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Regarding claim 5, Yemenicioglu in view of Bao discloses, The method ([0026]) of claim 1, wherein the first transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu) further comprises a first gate structure (first gate structure (210); FIG. 2; [0029], all of Bao) extending around a third quantity of sides (seven (7) sides; annotated FIG. 2 of Bao, above) of each of the first nanostructures (206a), and the second transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu) further comprises a second gate structure (second gate structure (210); FIG. 2; [0029], all of Bao) extending around a fourth quantity of sides (twelve (12) sides; annotated FIG. 2 of Bao, above) of each of the second nanostructures (206b), the fourth quantity being different than the third quantity (fourth quantity = 12 which is different than third quantity = 7; annotated FIG. 2 of Bao, above).
Regarding claim 6, Yemenicioglu in view of Bao discloses, an alternative embodiment of a device layout (device layout (150); FIG. 1C; [0043], all of Yemenicioglu) that includes a first cell (first cell (152); FIG. 1C; [0043], all of Yemenicioglu) defining a first transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu), the first transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu) comprising a first quantity of first nanostructures (first quantity of first nanostructures (166); FIG. 1C; [0043], all of Yemenicioglu); a second cell (second cell (154); FIG. 1C; [0043], all of Yemenicioglu) directly adjacent first cell (152), the second cell (154) defining a second transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu) and comprising a second quantity of second nanostructures (second quantity of second nanostructures (162); FIG. 1C; [0043], all of Yemenicioglu), and placing a third cell (third cell (156); FIG. 1C; [0043], all of Yemenicioglu) in the device layout (150) directly adjacent to the second cell (154), the third cell (156) defining a third transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu), the third transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu) comprising a third quantity of third nanostructures (third quantity of third nanostructures (158); FIG. 1C; [0043], all of Yemenicioglu), the third quantity [of third nanostructures (158)] being different than the second quantity [of second nanostructures (162)] and the first quantity [of first nanostructures (166)], as taught Bao ([0035]), so that the characteristics of third transistor of Yemenicioglu can be tuned based on the type of transistor device and/or current flow associated with the third transistor device type, as also taught by Bao ([0031]).
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Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yemenicioglu in view of Bao, as applied to claim 1 above, and further in view of US 2021/0202465 A1 (Wang).
Regarding claim 3, Yemenicioglu in view of Bao does not appear to explicitly disclose, wherein a first size of the first cell is different than a second size of the second cell.
However, in analogous art, Wang discloses that it is well known that a device layout (FIG. 1A) including a first cell (first cell (120); FIG. 1A; [0017]) and an adjacent second cell (second cell (122); FIG. 1A; [0017]) that are of different sizes (FIG. 1A). Wang also discloses that first cell (120) is a large cell with first dimension (first dimension (DL); FIG. 1A; [0027]) and that second cell (122) is a standard cell with second smaller dimension (second dimension (DS); FIG. 1A; [0027]), where Ds < DL ([0027]).
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Wang additionally discloses that the different sizes of first cell (120) and second cell (122) allow circuit packing density to be increased and device performance to be enhanced ([0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yemenicioglu, Bao, and Wang before him/her, that a first size of the first cell (102) of Yemenicioglu in view of Bao is different than a second size of the second cell (104) of Yemenicioglu in view of Bao, as taught by Wang, to allow circuit packing density to be increase and/or device performance to be enhanced, as also taught by Wang.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yemenicioglu in view of Bao, as applied to claim 1 above, and further in view of US 2020/0105752 A1 (Liaw).
Regarding claim 7, Yemenicioglu in view of Bao discloses, The method ([0026]) of claim 1, wherein:
the first transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu) is a first p-type transistor (annotated FIG. 1A of Yemenicioglu, above), the first cell (102) comprises a first n-type transistor (annotated FIG. 1A of Yemenicioglu, above), the first n-type transistor (annotated FIG. 1A of Yemenicioglu, above) comprises the first quantity of third nanostructures2 (first quantity of third nanostructures (112); FIG. 1A; [0036], all of Yemenicioglu); and
the second transistor (FIGs. 11A-11C; [0120], [0140], and [0143], all of Yemenicioglu) is a second p-type transistor (annotated FIG. 1A of Yemenicioglu, above), the second cell (104) comprises a second n-type transistor (annotated FIG. 1A of Yemenicioglu, above), the second n-type transistor (annotated FIG. 1A of Yemenicioglu, above) comprises the second quantity of fourth nanostructures3 (second quantity of fourth nanostructures (106); FIG. 1A; [0036], all of Yemenicioglu).
But Yemenicioglu in view of Bao does not appear to explicitly disclose,
a first width of the first nanostructures is different than a third width of the third nanostructures; and
a second width of the second nanostructures is different than a fourth width of the fourth nanostructures.
However, in analogous art, Liaw discloses, that it is well-known that a first transistor (first transistor (140); annotated FIG. 3, below; [0029]) can be predicably fabricated to include a first quantity of first nanostructures (first quantity of first nanostructures (142); annotated FIG. 3, below; [0035]), a second transistor (second transistor (140); annotated FIG. 3, below; [0029]) can be predicably fabricated to include a second quantity of second nanostructures (second quantity of second nanostructures (142); annotated FIG. 3, below; [0035]), a third transistor (third transistor (120); annotated FIG. 3, below; [0029]) can be predicably fabricated to include a third quantity of third nanostructures (third quantity of third nanostructures (122); annotated FIG. 3, below; [0034]), and a fourth transistor (fourth transistor (120); annotated FIG. 3, below; [0029]) can be predicably fabricated to include a fourth quantity of fourth nanostructures (fourth quantity of fourth nanostructures (122); annotated FIG. 3, below; [0034]).
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Liaw also discloses that it is well known that a first width (first width (W1); FIG. 3; [0035]) of the first nanostructures (142) can be predicably fabricated to be different ([0036]) than a third width (third width (W2); FIG. 3; [0034]) of the third nanostructures (122) and that a second width (second width (W1); FIG. 3; [0035]) of the second nanostructures (142) can be predicably fabricated to be different ([0036]) than a fourth width (fourth width (W2); FIG. 3; [0034]) of the fourth nanostructures (122). Liaw additionally discloses that different (i.e., wider) widths (W1) of first and second nanostructures (142) than widths (W2) of third and fourth nanostructures (122) provides higher drive current Ion for first and second transistors (140) making them more suitable for high-speed applications and that different (i.e., narrower) widths (W2) of third and fourth nanostructures (122) than widths (W1) of first and second nanostructures (142) provides lower leakage current and lower power consumption for third and fourth transistors (120) making them more suitable for low power and non-speed-critical applications, thereby providing sufficient differentiation between the performance of first and second transistors (140) from third and fourth transistors (120) ([0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yemenicioglu, Bao, and Liaw before him/her, that a first width of the first nanostructures (110) of Yemenicioglu in view of Bao is different than a third width of the third nanostructures (112) of Yemenicioglu in view of Bao, as taught by Liaw, thereby providing sufficient differentiation between the performance of the first p-type transistor (annotated FIG. 1A of Yemenicioglu, above) and the first n-type transistor (annotated FIG. 1A of Yemenicioglu, above) of Yemenicioglu in view of Bao, as also taught by Liaw; and a second width of the second nanostructures (108) of Yemenicioglu in view of Bao is different than a fourth width of the fourth nanostructures (106) of Yemenicioglu in view of Bao, as additionally taught by Liaw, thereby providing sufficient differentiation between the performance of the second p-type transistor (annotated FIG. 1A of Yemenicioglu, above) and the second n-type transistor (annotated FIG. 1A of Yemenicioglu, above) of Yemenicioglu in view of Bao, as further taught by Liaw.
Regarding claim 8, Yemenicioglu in view of Bao and further in view of Liaw does not appear to explicitly disclose, wherein the first width of the first nanostructures is different than the second width of the second nanostructures, and the third width of the third nanostructures is different than the fourth width of the fourth nanostructures.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yemenicioglu, Bao, and Liaw before him/her, that the first width of the first nanostructures (110) of Yemenicioglu in view of Bao is different than the second width of the second nanostructures (108) of Yemenicioglu in view of Bao to provide sufficient differentiation between the performance of the first p-type transistor (annotated FIG. 1A of Yemenicioglu, above) and the second p-type transistor (annotated FIG. 1A of Yemenicioglu, above) of Yemenicioglu in view of Bao, as taught by Liaw, and the third width of the third nanostructures (112) of Yemenicioglu in view of Bao is different than the fourth width of the fourth nanostructures (106) of Yemenicioglu in view of Bao to provide sufficient differentiation between the performance of the first n-type transistor (annotated FIG. 1A of Yemenicioglu, above) and the second n-type transistor (annotated FIG. 1A of Yemenicioglu, above) of Yemenicioglu in view of Bao, as also taught by Liaw.
Regarding claim 9, Yemenicioglu in view of Bao and further in view of Liaw discloses, The method ([0026]) of claim 8,4 wherein the first width of the first nanostructures (110) is the same as the second width of the second nanostructures (108) (annotated FIG. 1A of Yemenicioglu, above), and the third width of the third nanostructures (112) is the same as the fourth width of the fourth nanostructures (106) (annotated FIG. 1A of Yemenicioglu, above).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) US 2023/0084182 A1 (Hasan)—Discloses that it was well-known to one of ordinary skill in the art before the first effective filing date of the claimed invention that a method may predicably fabricate a first transistor (102) having a first quantity of nanostructures (112a) and a second transistor (104) having a second quantity of nanostructures (112b) (FIG. 1B). Also discloses, that the number of first quantity of nanostructures (112a) is different than the number of second quantity of nanostructures (112b) (FIG. 1B). Additionally discloses that widths of the first quantity of nanostructures (112a) differ and that widths of the second quantity of nanostructures (112b) differ.
(b) US 2023/0009388 A1 (Ji)—Discloses that it was well-known to one of ordinary skill in the art before the first effective filing date of the claimed invention that a method may predicably fabricate a plurality of respective first, second, third and fourth nanostructures (130A, 130B, 130C, and 130D) each of which has a different respective first, second, third, and fourth width (FIC 3C).
US 2020/0381432 A1 (Lee)—Discloses that it was well-known to one of ordinary skill in the art before the first effective filing date of the claimed invention that a method may include a layout (10) having a plurality of adjacent cells (FIG. 1) defining a first transistor (TR1) having a first quantity of first nanostructures (106a) (FIG. 2) and a second transistor (TR2) directly adjacent to first transistor (TR1) and having a second quantity of second nanostructures (106b) (FIG. 2) that is different than the first quantity of first nanostructures (106a). Lee also discloses that a width (W3a) of first quantity of first nanostructures (106a) is different that a width (W4a) of the second quantity of second nanostructures (106b)( FIG. 2).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703)756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Please see the rejection of claim 1 under 35 U.S.C. 112(b) for how this recited language is being interpreted for purpose of examination.
2 Please see objection to claim 7, above.
3 Please see objection to claim 7, above.
4 Please see objection to claim 9, above.