DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on January 14, 2026 was considered by the Examiner.
Response to Arguments
RE: the rejection of claim(s) 1-20 under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as Applicant’s amendments have prompted the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-8, 10-11, 13-18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20090294916A1 (“Ma”) in view of US6319450B1 (“Chua”).
RE: Claim 1, Ma discloses A semiconductor package (structure in FIGs. 1-2; FIG. 2 is a cross-section of FIG. 1, [0020]-[0021]), comprising:
a semiconductor substrate (combination of first two layers 10 from the top in FIG. 2, and optionally first two vias 12, first two metal pads 15, first two adhesive layers 16, and first two solder 13 from the top; wafer 10 is formed of silicon, [0030]; under a broad reasonable interpretation, the term “semiconductor substrate” is a substrate that includes semiconductor material and may include other materials, and is not necessarily considered a monolithic piece of semiconductor material); and
at least one semiconductor chip (remaining layers 10, vias 12, metal pads 15, adhesive layers 16, and solder 13 in FIG. 2) in contact with the semiconductor substrate, the at least one semiconductor chip comprising a first surface (top surface defined by third layer 10, third 15, third adhesive layer 16 from the top in FIG. 2) facing the semiconductor substrate, an opposite second surface (bottom surface of bottom 10), a die region (region between vias 12 and pads 15 and including vias 12 and pads 15, see Annotated FIG. 1 below; vias 120 in FIG. 1 correspond to vias 12 in FIG. 2 since FIG. 2 is a cross-section of FIG. 1), an edge region (region outside region between vias 12 and pads 15 in FIG. 2; see annotated FIG. 1) extending around the die region, and a plurality of air exhaust passages (air exhaust passages 18 shown in Annotated FIG. 1 below; 18 is labelled in FIG. 3 and included in FIGs. 1-2 though not labelled) extending from the die region to an outer surface of the edge region in the first surface (Ma discloses: An adhesive layer 16 is then applied to the exposed surface of the wafer 10 and is patterned as shown and described above with reference to FIGS. 1 to 3 such that an annular space 17 is defined around each metal pad 15. The patterning of the adhesive layer 16 will also include interconnecting channels 18 as shown in FIGS. 1 to 3 that interconnects the annular spaces 17 surrounding the metal pads 15 and which defines conduits connecting the annular spaces 17 to the edges of the wafer 10, [0031], see also [0027]; the process is repeated as often as required until the wafer stack is completed as shown in FIG. 12, [0032]; Accordingly, the channels 17, 18 are present in each layer 16 in FIG. 12 and therefore in each layer of FIGs. 1-2; FIG. 2 shows 17 is in surface defined by 10, 15, 16; Ma discloses in addition to providing connections between the annular spaces 17, there is also an interconnecting channel 18 that leads from each annular space 17 to the edge 19 of the stack, [0027]; a network of interconnecting channels are provided such that for every TSV, whether at an edge of the wafer or not, there exists a continuous path from the annular space 17 surrounding a TSV to an edge of the wafer 19, whether directly or via other annular spaces 17, [0028]; By patterning the adhesive layer channels are provided that enable gases released during out-gassing to escape, [0034]),
wherein each of the air exhaust passages comprises:
an inlet having a first passage area (Annotated FIG. 1 below shows each air exhaust passage includes an inlet having a first passage area); and
an outlet having a second passage area (Annotated FIG. 1 below shows each air exhaust passage includes an outlet having a second passage area), and
wherein the passage of the air exhaust is a cross-sectional area perpendicular to a length direction between the inlet and the outlet (the passage area would be a cross-sectional area perpendicular to the length direction between the inlet and outlet in Annotated FIG. 1 below).
Ma does not explicitly disclose:
the second passage area is greater than the first passage area;
wherein a passage area of an air exhaust passage connecting the inlet to the outlet increases along its length between the inlet and the outlet.
However, Ma discloses By patterning the adhesive layer channels are provided that enable gases released during out-gassing to escape, [0034].
In the same field of endeavor, Chua discloses A mold is provided having at least one vent hole that allows egress of air, Col. 2, lines 26-34.
Chua further discloses The vent 120 fans outward between an inside end 121 and an outside end 122 (best seen in FIGS. 3A and 4). The vent 120 has a cross section that increases in area from the inside end 121 to the outside end 122. The width of the vent 120 also increases in area from the inside end 121 to the outside end 122, Col. 3, lines 12-19, see FIGs. 3A and 4.
Chua further discloses The vent hole may have a shape of a trapezoidal prism, a truncated pyramid or a truncated cone, see abstract.
Accordingly, Chua teaches the passage area of an air vent connecting its inlet to its outlet increases along its length between the inlet and the outlet (the cross-sectional area would increase along the length of a trapezoidal prism, truncated pyramid or truncated cone between its inlet and outlet, see abstract in Chua), wherein the passage of the air exhaust is a cross-sectional area perpendicular to a length direction between the inlet and the outlet (the passage area would be a cross-sectional area perpendicular to a length direction between the inlet and outlet of the trapezoidal prism, truncated pyramid or truncated cone).
Chua further discloses for improving venting, the air vents may be widened to increase the cross-sectional area of the vent, Col.1, lines 61-65.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the plurality of air exhaust passages to each have a cross-sectional area that increases along its length from the inlet to the outlet as taught by Chua in order to improve venting.
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RE: Claim 3, Ma in view of Chua discloses The semiconductor package of claim 1, wherein each of the die region and the edge region has a rectangular shape in plan view (Annotated FIG. 1 of Ma below shows die region and edge region have rectangular shape; edge region defined by 115, 116, 118, 119),
each of the air exhaust passages extends from first corner regions of the die region to second corner regions of the edge region (Annotated FIG. 1 of Ma below shows channels 18 extend from corner regions of the die region to the second corner regions of the edge region; Ma discloses patterning of the adhesive layer 16 will also include interconnecting channels 18 as shown in FIGS. 1 to 3 that interconnects the annular spaces 17 surrounding the metal pads 15, [0031]; FIG. 3 shows channels 17, 18 formed in adhesive layer 16; Accordingly, the second corner regions would be formed in the adhesive layer 16 at the intersection of channels 18 with the edge region as shown in Annotated FIG. 1).
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RE: Claim 4, Ma in view of Chua discloses The semiconductor package of claim 1, wherein each of the die region and the edge region has a rectangular shape in plan view (Annotated FIG. 1 of Ma below shows die region and edge region have rectangular shape; edge region defined by 115, 116, 118, 119),
each of the air exhaust passages extends from first vertex regions of the die region to second vertex regions of the edge region (Annotated FIG. 1 below shows air exhaust passages 18 extend from first vertex regions of the die region to second vertex regions of the edge region; the term vertex is defined as “a point (as of an angle, polygon, polyhedron, graph, or network) that terminates a line or curve or comprises the intersection of two or more lines or curves,” see definition 2b in Merriam-Webster’s dictionary available at https://www.merriam-webster.com/dictionary/vertex, accessed on Sept. 4, 2025; Ma discloses patterning of the adhesive layer 16 will also include interconnecting channels 18 as shown in FIGS. 1 to 3 that interconnects the annular spaces 17 surrounding the metal pads 15, [0031]; FIG. 3 shows channels 17, 18 formed in adhesive layer 16; Accordingly, each channel 18 would be terminated at a first point at an inlet and a second point at an outlet along the adhesive layer 16; these first and second points along adhesive layer 16 correspond to the claimed first and second vertex regions under a broad reasonable interpretation).
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RE: Claim 5, Ma in view of Chua discloses The semiconductor package of claim 1, wherein the at least one semiconductor chip further comprises a plurality of second air exhaust passages that respectively branch from the air exhaust passages and extend to the outer surface of the edge region (Annotated FIG. 1 for claim 1 above shows second air exhaust passages respectively branch from the air exhaust passages 18 and extend to the outer surface of the edge region and include second outlets).
RE: Claim 6, Ma in view of Chua discloses The semiconductor package of claim 5, wherein each of the second air exhaust passages comprises:
a second inlet having a third passage area (Annotated FIG. 1 above for claim 1 shows each of the second air exhaust passages comprise a second inlet having a third passage area); and
a second outlet having a fourth passage area greater than the third passage area (In Annotated FIG. 1 for claim 1, Ma shows the second outlets of the channels 18 at the outermost circular edge of 100 have a cross-sectional area. This cross-sectional area is shown wider than the second inlets of 18 and therefore this cross-sectional area would be larger than the cross-sectional area perpendicular to sides of 18 at the second inlets).
RE: Claim 7, Ma in view of Chua discloses The semiconductor package of claim 1, wherein each of the air exhaust passages comprises a trench shape recessed in the first surface (Ma discloses An adhesive layer 16 is then applied to the exposed surface of the wafer 10 and is patterned as shown and described above with reference to FIGS. 1 to 3 such that an annular space 17 is defined around each metal pad 15. The patterning of the adhesive layer 16 will also include interconnecting channels 18 as shown in FIGS. 1 to 3, [0031]; Accordingly, 17, 18 are formed by the same patterning process; FIGs. 2-3 shows the patterning of the adhesive layer 16 forms a space 17 having a trench shape recessed in a top surface of adhesive 16; Accordingly, the patterning of the adhesive layer 16 would form channels 18 having a trench shape recessed in the first surface of adhesive 16).
RE: Claim 8, Ma in view of Chua discloses The semiconductor package of claim 1, wherein the semiconductor substrate further comprises a chip region (In Ma: the region of 10 between first two vias 12 from the top and optionally including first two pads 15 from top in FIG. 2; the die region in Annotated FIG. 1 for claim 1 above would correspond to the claimed chip region as the channels in FIG. 1 would be present in each layer 16 in FIG. 2 as discussed above for claim 1, see [0032]), an outermost edge region (region of 10 outside region of 10 between first two vias 12 from top, including portion of 17 on the left of leftmost 15 and portion of 17 on the right of rightmost 15; the edge region in Annotated FIG. 1 for claim 1 would correspond to the claimed edge region as the channels in FIG. 1 would be present in each layer 16 in FIG. 2 as discussed above) extending around the chip region, and a plurality of third air exhaust passages extending from the chip region to a second outer surface of the outermost edge region (Annotated FIG. 1 for claim 1 shows third air exhaust passages 18 with third inlets and third outlets, the third air exhaust passages 18 extending from the die region to a second outer surface of the outermost edge region), and wherein the third air exhaust passage comprises:
a third inlet having a fifth passage area (Annotated FIG. 1 for claim 1 shows third inlet having a fifth passage area); and
a third outlet having a sixth passage area greater than the fifth passage area (Annotated FIG. 1 for claim 1 shows third outlet having a sixth passage area larger than the fifth passage area as the sixth passage area is shown wider than that of the fifth passage area).
RE: Claim 10, Ma in view of Chua discloses The semiconductor package of claim 1, wherein the semiconductor substrate comprises a semiconductor wafer (Ma discloses wafer 10 is formed of silicon, [0030]).
RE: Claim 11, Ma discloses A semiconductor package (structure in FIGs. 1-2; FIG. 2 is a cross-section of FIG. 1, [0020]-[0021]), comprising:
a semiconductor substrate (combination of first two layers 10 from the top in FIG. 2, and optionally first two vias 12, first two metal pads 15, first two adhesive layers 16, and first two solder 13 from the top; wafer 10 is formed of silicon, [0030]; under a broad reasonable interpretation, the term “semiconductor substrate” is a substrate that includes semiconductor material and may include other materials, and is not necessarily considered a monolithic piece of semiconductor material); and
at least one semiconductor chip (remaining layers 10, vias 12, metal pads 15, adhesive layers 16, and solder 13 in FIG. 2) on the semiconductor substrate (the third adhesive layer 16 is on bottom surface of second layer 10 from the top; alternatively, when FIG. 2 is flipped, the remaining layers 10, 12, 15, 16, 13 would be on the first two layers 10 from the top in FIG. 2), the at least one semiconductor chip comprising a first surface (top surface defined by third 10, third 15, third adhesive layer 16 from the top in FIG. 2) in contact with the semiconductor substrate, an opposite second surface (bottom surface of bottom 10), a die region (region of 10 between vias 12, see annotated FIG. 1; vias 120 in FIG. 1 correspond to vias 12 in FIG. 2 since FIG. 2 is a cross-section of FIG. 1), an edge region (region of 10 outside region between vias 12 in FIG. 2; see annotated FIG. 1) extending around the die region, and a plurality of air exhaust passages (air exhaust passages 18 shown in Annotated FIG. 1 below; 18 is labelled in FIG. 3 and included in FIGs. 1-2 though not labelled) extending from the die region to an outer surface of the edge region (Ma discloses: An adhesive layer 16 is then applied to the exposed surface of the wafer 10 and is patterned as shown and described above with reference to FIGS. 1 to 3 such that an annular space 17 is defined around each metal pad 15. The patterning of the adhesive layer 16 will also include interconnecting channels 18 as shown in FIGS. 1 to 3 that interconnects the annular spaces 17 surrounding the metal pads 15 and which defines conduits connecting the annular spaces 17 to the edges of the wafer 10, [0031], see also [0027]; the process is repeated as often as required until the wafer stack is completed as shown in FIG. 12, [0032]; Accordingly, the channels 17, 18 are present in each layer 16 in FIG. 12 and therefore in each layer of FIGs. 1-2; FIG. 2 shows 17 is in surface defined by 10, 15, 16; Ma discloses in addition to providing connections between the annular spaces 17, there is also an interconnecting channel 18 that leads from each annular space 17 to the edge 19 of the stack, [0027]; a network of interconnecting channels are provided such that for every TSV, whether at an edge of the wafer or not, there exists a continuous path from the annular space 17 surrounding a TSV to an edge of the wafer 19, whether directly or via other annular spaces 17, [0028]; By patterning the adhesive layer channels are provided that enable gases released during out-gassing to escape, [0034]),
each air exhaust passage comprising an inlet having a first passage area and an outlet having a second passage area (Annotated FIG. 1 below shows each air exhaust passage includes an inlet having a first passage area and an outlet having a second passage area, and
wherein the passage of the air exhaust is a cross-sectional area perpendicular to a length direction between the inlet and the outlet (the passage area would be a cross-sectional area perpendicular to the length direction between the inlet and outlet in Annotated FIG. 1 below).
Ma does not explicitly disclose the second passage area of the outlet is greater than the first passage area of the inlet;
wherein a passage area of an air exhaust passage connecting the inlet to the outlet increases along its length between the inlet and the outlet.
However, Ma discloses By patterning the adhesive layer channels are provided that enable gases released during out-gassing to escape, [0034].
In the same field of endeavor, Chua discloses A mold is provided having at least one vent hole that allows egress of air, Col. 2, lines 26-34.
Chua further discloses The vent 120 fans outward between an inside end 121 and an outside end 122 (best seen in FIGS. 3A and 4). The vent 120 has a cross section that increases in area from the inside end 121 to the outside end 122. The width of the vent 120 also increases in area from the inside end 121 to the outside end 122, Col. 3, lines 12-19, see FIGs. 3A and 4.
Chua further discloses The vent hole may have a shape of a trapezoidal prism, a truncated pyramid or a truncated cone, see abstract.
Accordingly, Chua teaches the passage area of an air vent connecting its inlet to its outlet increases along its length between the inlet and the outlet (the cross-sectional area would increase along the length of a trapezoidal prism, truncated pyramid or truncated cone between its inlet and outlet, see abstract in Chua), wherein the passage of the air exhaust is a cross-sectional area perpendicular to a length direction between the inlet and the outlet (the passage area would be a cross-sectional area perpendicular to a length direction between the inlet and outlet of the trapezoidal prism, truncated pyramid or truncated cone).
Chua further discloses for improving venting, the air vents may be widened to increase the cross-sectional area of the vent, Col.1, lines 61-65.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the plurality of air exhaust passages to each have a cross-sectional area that increases along its length from the inlet to the outlet as taught by Chua in order to improve venting.
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RE: Claim 13, Ma in view of Chua discloses The semiconductor package of claim 11, wherein each of the die region and the edge region has a rectangular shape in plan view (Annotated FIG. 1 of Ma below shows die region and edge region have rectangular shape; edge region defined by 115, 116, 118, 119),
wherein each of the air exhaust passages extends from first corner regions of the die region to second corner regions of the edge region (Annotated FIG. 1 of Ma below shows channels 18 extend from corner regions of the die region to the second corner regions of the edge region; Ma discloses patterning of the adhesive layer 16 will also include interconnecting channels 18 as shown in FIGS. 1 to 3 that interconnects the annular spaces 17 surrounding the metal pads 15, [0031]; FIG. 3 shows channels 17, 18 formed in adhesive layer 16; Accordingly, the second corner regions would be formed in the adhesive layer 16 at the intersection of channels 18 with the edge region as shown in Annotated FIG. 1).
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RE: Claim 14, Ma in view of Chua discloses The semiconductor package of claim 11, wherein each of the die region and the edge region has a rectangular shape in plan view (Annotated FIG. 1 of Ma below shows die region and edge region have rectangular shape; edge region defined by 115, 116, 118, 119),
wherein each of the air exhaust passages extends from first vertex regions of the die region to second vertex regions of the edge region (Annotated FIG. 1 below shows air exhaust passages 18 extend from first vertex regions of the die region to second vertex regions of the edge region; the term vertex is defined as “a point (as of an angle, polygon, polyhedron, graph, or network) that terminates a line or curve or comprises the intersection of two or more lines or curves,” see definition 2b in Merriam-Webster’s dictionary available at https://www.merriam-webster.com/dictionary/vertex, accessed on Sept. 4, 2025; Ma discloses patterning of the adhesive layer 16 will also include interconnecting channels 18 as shown in FIGS. 1 to 3 that interconnects the annular spaces 17 surrounding the metal pads 15, [0031]; FIG. 3 shows channels 17, 18 formed in adhesive layer 16; Accordingly, each channel 18 would be terminated at a first point at an inlet and a second point at an outlet along the adhesive layer 16; these first and second points along adhesive layer 16 correspond to the claimed first and second vertex regions under a broad reasonable interpretation).
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RE: Claim 15, Ma in view of Chua discloses The semiconductor package of claim 11, wherein the at least one semiconductor chip further comprises a plurality of second air exhaust passages that branch from the air exhaust passages and extend to the outer surface of the edge region (Annotated FIG. 1 for claim 11 above shows second air exhaust passages respectively branch from the air exhaust passages 18 and extend to the outer surface of the edge region and include second outlets).
RE: Claim 16, Ma in view of Chua discloses The semiconductor package of claim 15, wherein each of the second air exhaust passages comprises:
a second inlet having a third passage area (Annotated FIG. 1 above for claim 11 shows each of the second air exhaust passages comprise a second inlet having a third passage area); and
a second outlet having a fourth passage area greater than the third passage area (In Annotated FIG. 1 for claim 11, Ma shows the second outlets of the channels 18 at the outermost circular edge of 100 have a cross-sectional area. This cross-sectional area is shown wider than the second inlets of 18 and therefore this cross-sectional area would be larger than the cross-sectional area perpendicular to sides of 18 at the second inlets).
RE: Claim 17, Ma in view of Chua discloses The semiconductor package of claim 11, wherein each air exhaust passage comprises a trench shape recessed in the first surface (Ma discloses An adhesive layer 16 is then applied to the exposed surface of the wafer 10 and is patterned as shown and described above with reference to FIGS. 1 to 3 such that an annular space 17 is defined around each metal pad 15. The patterning of the adhesive layer 16 will also include interconnecting channels 18 as shown in FIGS. 1 to 3, [0031]; Accordingly, 17, 18 are formed by the same patterning process; FIGs. 2-3 shows the patterning of the adhesive layer 16 forms a space 17 having a trench shape recessed in a top surface of adhesive 16; Accordingly, the patterning of the adhesive layer 16 would form channels 18 having a trench shape recessed in the first surface of adhesive 16).
RE: Claim 18, Ma in view of Chua discloses The semiconductor package of claim 11, wherein the semiconductor substrate further comprises a chip region (In Ma: the region of 10 between first two vias 12 from the top and optionally including first two pads 15 from top in FIG. 2; the die region in Annotated FIG. 1 for claim 11 above would correspond to the claimed chip region as the channels in FIG. 1 would be present in each layer 16 in FIG. 2 as discussed above for claim 11, see [0032]), an outermost edge region (region of 10 outside region of 10 between first two vias 12 from top, including portion of 17 on the left of leftmost 15 and portion of 17 on the right of rightmost 15; the edge region in Annotated FIG. 1 for claim 11 would correspond to the claimed edge region as the channels in FIG. 1 would be present in each layer 16 in FIG. 2 as discussed above) extending around the chip region, and a plurality of third air exhaust passages extending from the chip region to a second outer surface of the outermost edge region (Annotated FIG. 1 for claim 11 shows third air exhaust passages 18 with third inlets and third outlets, the third air exhaust passages 18 extending from the die region to a second outer surface of the outermost edge region), and wherein the third air exhaust passage comprises:
a third inlet having a fifth passage area (Annotated FIG. 1 for claim 11 shows third inlet having a fifth passage area); and
a third outlet having a sixth passage area greater than the fifth passage area (Annotated FIG. 1 for claim 11 shows third outlet having a sixth passage area larger than the fifth passage area as the sixth passage area is shown wider than that of the fifth passage area).
RE: Claim 20, Ma discloses A semiconductor package (structure in FIGs. 1-2; FIG. 2 is a cross-section of FIG. 1, [0020]-[0021]), comprising:
a first semiconductor substrate (combination of first two layers 10 from the top in FIG. 2, and optionally first two vias 12, first two metal pads 15, first two adhesive layers 16, and first two solder 13 from the top; wafer 10 is formed of silicon, [0030]; under a broad reasonable interpretation, the term “semiconductor substrate” is a substrate that includes semiconductor material and may include other materials, and is not necessarily considered a monolithic piece of semiconductor material); and
a second semiconductor substrate (remaining layers 10, vias 12, metal pads 15, adhesive layers 16, and solder 13 in FIG. 2) on the first semiconductor substrate (the third adhesive layer 16 is on bottom surface of second layer 10 from the top; alternatively, when FIG. 2 is flipped, the remaining layers 10, 12, 15, 16, 13 would be on the first two layers 10 from the top in FIG. 2), the second semiconductor substrate comprising a chip region (region of 10 between vias 12, see Annotated FIG. 1; vias 120 in FIG. 1 correspond to vias 12 in FIG. 2 since FIG. 2 is a cross-section of FIG. 1), an outermost edge region (region of 10 outside region between vias 12 in FIG. 2; see Annotated FIG. 1) extending around the chip region, and a plurality of air exhaust passages (air exhaust passages 18 shown in Annotated FIG. 1 below; 18 is labelled in FIG. 3 and included in FIGs. 1-2 though not labelled) recessed from a first surface (top surface of third adhesive layer 16 from the top in FIG. 2) that faces the first semiconductor substrate and extending from the chip region to an outer surface of the outermost edge region (Ma discloses: An adhesive layer 16 is then applied to the exposed surface of the wafer 10 and is patterned as shown and described above with reference to FIGS. 1 to 3 such that an annular space 17 is defined around each metal pad 15. The patterning of the adhesive layer 16 will also include interconnecting channels 18 as shown in FIGS. 1 to 3 that interconnects the annular spaces 17 surrounding the metal pads 15 and which defines conduits connecting the annular spaces 17 to the edges of the wafer 10, [0031], see also [0027]; the process is repeated as often as required until the wafer stack is completed as shown in FIG. 12, [0032]; Accordingly, the channels 17, 18 are present in each layer 16 in FIG. 12 and therefore in each layer of FIGs. 1-2; FIG. 2 shows 17 is in surface defined by 10, 15, 16; Ma discloses in addition to providing connections between the annular spaces 17, there is also an interconnecting channel 18 that leads from each annular space 17 to the edge 19 of the stack, [0027]; a network of interconnecting channels are provided such that for every TSV, whether at an edge of the wafer or not, there exists a continuous path from the annular space 17 surrounding a TSV to an edge of the wafer 19, whether directly or via other annular spaces 17, [0028]; By patterning the adhesive layer channels are provided that enable gases released during out-gassing to escape, [0034]; Accordingly, 17, 18 are formed by the same patterning process used to pattern the adhesive layer 16; FIGs. 2-3 shows the patterning of the adhesive layer 16 forms a space 17 having a trench shape recessed in a top surface of adhesive 16; Accordingly, the patterning of the adhesive layer 16 would form channels 18 having a trench shape recessed in the first surface of adhesive 16),
wherein each of the air exhaust passages comprises:
an inlet having a first passage area (Annotated FIG. 1 below shows each air exhaust passage includes an inlet having a first passage area); and
an outlet having a second passage area (Annotated FIG. 1 below shows each air exhaust passage includes an outlet having a second passage area), and
wherein the passage of the air exhaust is a cross-sectional area perpendicular to a length direction between the inlet and the outlet (the passage area would be a cross-sectional area perpendicular to the length direction between the inlet and outlet in Annotated FIG. 1 below).
Ma does not explicitly disclose:
the second passage area of the outlet is greater than the first passage area of the inlet;
wherein a passage area of an air exhaust passage connecting the inlet to the outlet increases along its length between the inlet and the outlet.
However, Ma discloses By patterning the adhesive layer channels are provided that enable gases released during out-gassing to escape, [0034].
In the same field of endeavor, Chua discloses A mold is provided having at least one vent hole that allows egress of air, Col. 2, lines 26-34.
Chua further discloses The vent 120 fans outward between an inside end 121 and an outside end 122 (best seen in FIGS. 3A and 4). The vent 120 has a cross section that increases in area from the inside end 121 to the outside end 122. The width of the vent 120 also increases in area from the inside end 121 to the outside end 122, Col. 3, lines 12-19, see FIGs. 3A and 4.
Chua further discloses The vent hole may have a shape of a trapezoidal prism, a truncated pyramid or a truncated cone, see abstract.
Accordingly, Chua teaches the passage area of an air vent connecting its inlet to its outlet increases along its length between the inlet and the outlet (the cross-sectional area would increase along the length of a trapezoidal prism, truncated pyramid or truncated cone between its inlet and outlet, see abstract in Chua), wherein the passage of the air exhaust is a cross-sectional area perpendicular to a length direction between the inlet and the outlet (the passage area would be a cross-sectional area perpendicular to a length direction between the inlet and outlet of the trapezoidal prism, truncated pyramid or truncated cone).
Chua further discloses for improving venting, the air vents may be widened to increase the cross-sectional area of the vent, Col.1, lines 61-65.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the plurality of air exhaust passages to each have a cross-sectional area that increases along its length from the inlet to the outlet as taught by Chua in order to improve venting.
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Claim(s) 2, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Chua as applied to claim 1 or 11 above, and further in view of US20130069205A1 to Ning et al. (hereinafter “Ning”).
RE: Claim 2, Ma in view of Chua does not explicitly disclose The semiconductor package of claim 1, wherein the air exhaust passages are provided in a scribe lane region of the at least one semiconductor chip inside the edge region.
However, Ma discloses four chips are divided by mutually perpendicular main rows 114-119 that are channels formed by patterning the adhesive and which lead to the edge of the wafer, [0025], see FIG. 1.
Ma further discloses Following the solder bonding process the wafer stack will be subject to a conventional singularity process, [0035]. Accordingly, Ma discloses that the wafer stack is subjected to singulation.
In the same field of endeavor, Ning discloses Since the grooves are formed along the scribe lane areas, the mechanical stress that is generated between a blade and a semiconductor wafer during the die sawing process is reduced, which provides smoother die edges and reduces chippings or cracks occurring during the die sawing process, [0048].
FIG. 4A in Ning shows scribe lane areas 120 separating chips 110.
Ning further discloses after forming the above-described groove structure, cutting may be performed along the grooves so as to singulate the plurality of dies 110 from each other, [0070].
Accordingly, it would have been obvious to one of ordinary skill in the art to introduce scribe lane areas so that the air exhaust channels 18 would be in the scribe lane areas as taught by Ning in order to reduce mechanical stress generated during the singulation process.
RE: Claim 12, Ma in view of Chua does not explicitly disclose The semiconductor package of claim 11, wherein the air exhaust passages are provided in a scribe lane region of the at least one semiconductor chip inside the edge region.
However, Ma discloses four chips are divided by mutually perpendicular main rows 114-119 that are channels formed by patterning the adhesive and which lead to the edge of the wafer, [0025], see FIG. 1.
Ma further discloses Following the solder bonding process the wafer stack will be subject to a conventional singularity process, [0035]. Accordingly, Ma discloses that the wafer stack is subjected to singulation.
In the same field of endeavor, Ning discloses Since the grooves are formed along the scribe lane areas, the mechanical stress that is generated between a blade and a semiconductor wafer during the die sawing process is reduced, which provides smoother die edges and reduces chippings or cracks occurring during the die sawing process, [0048].
FIG. 4A in Ning shows scribe lane areas 120 separating chips 110.
Ning further discloses after forming the above-described groove structure, cutting may be performed along the grooves so as to singulate the plurality of dies 110 from each other, [0070].
Accordingly, it would have been obvious to one of ordinary skill in the art to introduce scribe lane areas so that the air exhaust channels 18 would be in the scribe lane areas as taught by Ning in order to reduce mechanical stress generated during the singulation process.
Claim(s) 9, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Chua as applied to claim 1 or 11 above, and further in view of US20150001688A1 (“Iguchi”).
RE: Claim 9, Ma in view of Chua does not explicitly disclose The semiconductor package of claim 1, wherein a ratio of the second passage area to the first passage area is within a range of 1.1 to 3.
However, Chua discloses the vent has a width of 0.70 mm at its inside end, and a depth of 0.035 mm, Col. 3, lines 20-22.
In the same field of endeavor, Iguchi discloses the width of the groove 105 on the outer circumferential side of the rib 101 is 0.2 mm greater than that on the inner circumferential side and increases from the inside to the outside, [0054].
It would have been obvious to one of ordinary skill in the art to make the width at the outlet 0.9mm which would be 0.2mm greater than the width 0.7mm at the inlet as taught by Iguchi in order to improve ventilation. As a result, the ratio of the second passage area to the first passage area would be 0.9 / 0.7 = 1.29.
RE: Claim 19, Ma in view of Chua does not explicitly disclose The semiconductor package of claim 11, wherein a ratio of the second passage area to the first passage area is within a range of 1.1 to 3.
However, Chua discloses the vent has a width of 0.70 mm at its inside end, and a depth of 0.035 mm, Col. 3, lines 20-22.
In the same field of endeavor, Iguchi discloses the width of the groove 105 on the outer circumferential side of the rib 101 is 0.2 mm greater than that on the inner circumferential side and increases from the inside to the outside, [0054].
It would have been obvious to one of ordinary skill in the art to make the width at the outlet 0.9mm which would be 0.2mm greater than the width 0.7mm at the inlet as taught by Iguchi in order to improve ventilation. As a result, the ratio of the second passage area to the first passage area would be 0.9 / 0.7 = 1.29.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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