DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 12, and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 6 and 12, they are dependent on a canceled claim.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Allowable Subject Matter
Claims 1-4, 8-11, 14-16, and 18-20 are allowed.
Regarding claim 1, the closest prior art of record, LEE et al. (US PG Pub 2021/0074679), either singularly or in combination, does not disclose or suggest the combination of limitations including “A semiconductor package comprising:
a package substrate;
a first semiconductor chip disposed over the package substrate;
a second semiconductor chip stacked over the first semiconductor chip;
a third semiconductor chip stacked over the second semiconductor chip; and
a fourth semiconductor chip stacked over the third semiconductor chip,
wherein each of the first and second semiconductor chips comprises:
a chip body;
first chip pads disposed in a first region of a surface of the chip body along a first edge line of the chip body; and
second chip pads disposed in a second region of the surface of the chip body along a second edge line of the chip body intersecting the first edge line,
wherein the first chip pads of the first semiconductor chip and the first chip pads of the second semiconductor chip are disposed at opposite sides from each other over the package substrate,
wherein the second chip pads of the first semiconductor chip and the second chip pads of the second semiconductor chip are disposed at opposite sides from each other over the package substrate, and
wherein the second semiconductor chip is disposed to be offset with respect to the first semiconductor chip to expose the first chip pads and the second chip pads of the first semiconductor chip, and
wherein each of the third and fourth semiconductor chips includes:
a chip body;
first chip pads disposed in a first region of a surface of the chip body along a first edge line of the chip body; and
second chip pads disposed in a second region of the surface of the chip body along a second edge line of the chip body intersecting the first edge line, and
wherein the third semiconductor chip and the fourth semiconductor chip are disposed to be offset with respect to the first semiconductor chip and the second semiconductor chip, respectively,
wherein the first chip pads of the third semiconductor chip and the first chip pads of the fourth semiconductor chip are disposed at opposite sides from each other over the package substrate, and
wherein the second chip pads of the third semiconductor chip and the second chip pads of the fourth semiconductor chip are disposed at opposite sides from each other over the package substrate”.
Regarding claim 14, the closest prior art of record, LEE et al. (US PG Pub 2021/0074679), either singularly or in combination, does not disclose or suggest the combination of limitations including “A semiconductor package comprising:
a package substrate;
first and second semiconductor chips stacked over the package substrate;
a third semiconductor chip stacked over the second semiconductor chip; and
a fourth semiconductor chip stacked over the third semiconductor chip,
wherein each of the first and second semiconductor chips comprises:
a chip body;
first chip pads disposed in a first region of a surface of the chip body along a first edge line of the chip body; and
second chip pads disposed in a second region of the surface of the chip body along a second edge line of the chip body intersecting the first edge line, and
wherein the second semiconductor chip, after being substantially rotated by 1800 with respect to a center of the second semiconductor chip while overlapping with the first semiconductor chip, is offset in a first direction parallel to the first edge line of the first semiconductor chip and offset in a second direction parallel to the second edge line of the first semiconductor chip, and
wherein each of the third and fourth semiconductor chips includes:
a chip body;
first chip pads disposed in a first region of a surface of the chip body along a first edge line of the chip body; and
second chip pads disposed in a second region of the surface of the chip body along a second edge line of the chip body intersecting the first edge line, and
wherein the third semiconductor chip and the fourth semiconductor chip are disposed to be offset with respect to the first semiconductor chip and the second semiconductor chip, respectively,
wherein the first chip pads of the third semiconductor chip and the first chip pads of the fourth semiconductor chip are disposed at opposite sides from each other over the package substrate, and
wherein the second chip pads of the third semiconductor chip and the second chip pads of the fourth semiconductor chip are disposed at opposite sides from each other over the package substrate”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817