DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 13 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 13 recites “the area ratio is larger than 3.1 and smaller than 4.7” which repeats the same limitation in line 2 of claim 8. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 6-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakano et al. (Pub. No.: US 2019/0355718 A1), hereinafter as Nakano.
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Regarding claim 1, Nakano discloses a semiconductor device in Figs. 1-2 and 18, comprising: a transistor portion (transistor region 12) provided in a semiconductor substrate (substrate 700) (see Figs. 1-2, 18 and [0027], [0056]); and a diode portion (a diode region 14) provided in the semiconductor substrate (see [0027]), wherein an area ratio of an area of the transistor portion (illustrated by larger rectangular region in annotated Fig. 1 above) to an area of the diode portion (illustrated by smaller rectangular region in annotated Fig. 1 above) on a front surface of the semiconductor substrate is larger than 3.1 and smaller than 4.7 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (because claim does not further limit how the areas of the transistor portion and diode portion being measured, the areas of the transistor portion and diode portions can be chosen to meet the ratio requirement).
Regarding claim 2, Nakano discloses the semiconductor device according to claim 1, wherein the area ratio is larger than 3.2 and smaller than 4.0 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 3, Nakano discloses the semiconductor device according to claim 1, wherein the area ratio is larger than 3.4 and smaller than 3.8 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 4, Nakano discloses the semiconductor device according to claim 1, wherein the area ratio is 3.6 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 6, Nakano discloses the semiconductor device according to claim 1, comprising: a front surface electrode (upper electrode 9) electrically connected to the transistor portion and the diode portion above the semiconductor substrate (see Figs. 2, 18 and [0056]).
Regarding claim 7, Nakano discloses a semiconductor module in Figs. 1-2 and 18, comprising: a semiconductor device including a transistor portion (transistor region 12) and a diode portion (a diode region 14) provided in a semiconductor substrate in a semiconductor substrate (substrate 700) (see Figs. 1-2, 18 and [0027], [0056]); an external connection terminal (wiring member 10) electrically connected to the semiconductor device (see Fig. 2 and [0027]); and a coupling portion (wiring member) for electrically connecting the semiconductor device and the external connection terminal (external circuit) (see Fig. 2 and [0035-0036]), wherein the coupling portion is in plane contact with a front surface electrode (upper electrode 9) of the semiconductor device at a predetermined junction surface (junction surface between upper electrode 9 and joint member 20), and an area ratio of an area of the transistor portion (illustrated by larger rectangular region in annotated Fig. 1 above) to an area of the diode portion (illustrated by smaller rectangular region in annotated Fig. 1 above) on a front surface of the semiconductor substrate is larger than 2.8 and smaller than 4.7 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (because claim does not further limit how the areas of the transistor portion and diode portion being measured, the areas of the transistor portion and diode portions can be chosen to meet the ratio requirement).
Regarding claim 8, Nakano discloses the semiconductor module according to claim 7, wherein the area ratio is larger than 3.1 and smaller than 4.7 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 9, Nakano discloses the semiconductor module according to claim 7, wherein the area ratio is larger than 3.2 and smaller than 4.0 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 10, Nakano discloses the semiconductor module according to claim 7, wherein the area ratio is larger than 3.4 and smaller than 3.8 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 11, Nakano discloses the semiconductor module according to claim 7, wherein the area ratio is 3.6 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 12, Nakano discloses the semiconductor module according to claim 7, wherein the area ratio of the transistor portion to the diode portion is an area ratio of the transistor portion to the diode portion on a front surface of the semiconductor substrate (see annotated Fig. 1, 2 and 18).
Regarding claim 13, Nakano discloses the semiconductor module according to claim 8, wherein the area ratio is larger than 3.1 and smaller than 4.7 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 14, Nakano discloses the semiconductor module according to claim 8, wherein the area ratio is larger than 3.2 and smaller than 4.0 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 15, Nakano discloses the semiconductor module according to claim 8, wherein the area ratio is larger than 3.4 and smaller than 3.8 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 16, Nakano discloses the semiconductor module according to claim 7, wherein the area ratio of the transistor portion to the diode portion is an area ratio of a junction area between the transistor portion and the coupling portion (junction area between flat-plate portion 10a and the illustrated area of transistor portion 12) to a junction area between the diode portion and the coupling portion (junction area between flat-plate portion 10a and the illustrated area of diode region 14) (the illustrated areas of transistor region 12 and diode region 14 are the same junction areas between the transistor portion and joint member 20 and between the diode portion and the joint member 20) (see annotated Fig. 1 above and Fig. 2).
Regarding claim 17, Nakano discloses the semiconductor module according to claim 16, wherein the area ratio is larger than 3.1 and smaller than 4.7 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 18, Nakano discloses the semiconductor module according to claim 16, wherein the area ratio is larger than 3.2 and smaller than 4.0 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 19, Nakano discloses the semiconductor module according to claim 16, wherein the area ratio is larger than 3.4 and smaller than 3.8 (the illustrated area of the transistor region 12 is selected to be 3.6 times larger than the illustrated area of the diode region 14 for making the ratio to be 3.6) (see annotated Fig. 1 above).
Regarding claim 20, Nakano discloses the semiconductor module according to claim 16, wherein the coupling portion is a lead frame, a ribbon, or a clip (wiring member 10 can be lead frame, a clip or ribbon) (see Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano et al. (Pub. No.: US 2019/0355718 A1), hereinafter as Nakano as applied to claim 1 above, and further in view of YAMANO et al. (Pub. No.: US 2019/0287964 A1), hereinafter as Yamano.
Regarding claim 5, Nakano discloses the semiconductor device according to claim 1, the transistor portion and the diode portion are arrayed alternately in an array direction (y direction) (see Fig. 1-2). However, Nakano fails to disclose wherein the transistor portion and the diode portion include a plurality of trench portions arrayed in a predetermined array direction, and a width of the diode portion sandwiched between the transistor portions in the array direction is 200 µm or more.
Yamano discloses a semiconductor device in Fig. 1-2 comprising: a transistor portion (transistor portion 70) and a diode portion (diode portion 80) include a plurality of trench portions (gate trench portions 40 and dummy trench portion 30) arrayed in a predetermined array direction (x-direction) (see Fig. 2 and [0083-0084]), the transistor portion and the diode portion are arrayed alternately in the array direction (alternating in x-direction) (see Fig. 2), and a width of the diode portion (width D2) sandwiched between the transistor portions in the array direction is 200 µm or more (320 µm or less) (see Fig. 2 and [0088]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the plurality of trench portions and the dimension of the width of the diode portion of Yamano into the semiconductor device of Nakano because Nakano discloses the semiconductor device can also be manufacturing with trench structure (see Nakano and [0058]) and the modified structure would provide lower on-resistance and better performance for high-performance power devices.
Allowable Subject Matter
Claims 15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having: a reverse conducting type device with a shorted collector layer arranged at the second surface between the collector electrode and the buffer layer, wherein the shorted collector layer is formed by a pattern of first and second conductivity type regions as in claim 15; and wherein: a first edge of the second base layer is aligned in the second dimension with the first edge of the source region; a channel is formable on the lateral walls of the trench regions because of the highly doped second base region that prevents a vertical channel from forming between the emitter electrode, the source region, the first base layer, and the drift layer as recited in claim 18. Claims 5-10 depend on claim 2, and therefore also include said claimed limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818