Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Taking claim 1 as exemplary of claims 1 and 15-16, the boundaries of claim scope are not clear. It is not clear which limitation “using FIB editing” (line 6; see, also, claim 13) is referring to, is it a respective metal pad, one of the functional nodes, otherwise? In other words, the preamble states “debugging by FIB editing” yet this limitation merely recites using without any clear context. There is no antecedent basis for “selected BFEs” (line 9; see, also, claims 9-10) or “analysis” (line 9; see, also, claim 10), thus, what is intended by routing circuitry, configured to route for analysis is not particularly clear. Therefore, the claim is incomplete, vague and indefinite.
Taking claim 14 as exemplary of claims 14 and 18-19, the boundaries of claim scope are not clear. There is no antecedent basis for “supply-path circuit” (lines 2-3), thus, what is intended by at least partially overlaps is not particularly clear. Therefore, the claim is incomplete, vague and indefinite.
The remaining claims, although not specifically mentioned, are rejected for incorporating the indefiniteness of their respective base claims by dependency.
The following rejections are based on the Examiner’s best interpretation of the claims in view of the indefiniteness identified above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9 and 13-19 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Tsai [US 2005/0224950 A1].
As per claim 1, an Integrated Circuit (IC) designed for debugging by Focused Ion Beam (FIB) editing [paragraph 0002 an integrated circuit adapted for FIB debug], the IC comprising:
functional circuitry comprising functional nodes [paragraph 0024 previous stage circuit (not shown) and a next stage circuit (not shown); paragraph 0005 standard cells];
a network of Basic FIB elements (BFEs) [paragraph 0022 spare cell 220, only one element is depicted for simplicity of understanding the invention, it is inherent that a network is present in an integrated circuit], each comprising a respective metal pad configured to be connected to one of the functional nodes using FIB editing [paragraph 0023 any of terminal pads 231-234, paragraph 0024 terminal pad 254 or 234]; and
routing circuitry, configured to route one or more selected BFEs for analysis [paragraph 0022 coupled by the via structure, paragraph 0023 the via structure means a structure to electrically connect, Because the spare cell is prepared for debug, paragraph 0024 exemplary FIB debug for the integrated circuit].
2. The IC according to claim 1, wherein each BFE among one or more of the BFEs further comprises a respective supply-path circuit configured to provide a galvanic path between the BFE and a supply input of the IC [paragraph 0023 coupled to the system power voltage VCC by the via structure].
3. The IC according to claim 2, wherein the supply-path circuit comprises a passive resistor that is coupled to a supply rail of the IC [paragraph 0022 a preset electrical function, passive resistors and supply rails are inherent to integrated circuits].
4. The IC according to claim 2, wherein the supply-path circuit comprises an active resistance path to a supply rail of the IC [paragraph 0022 a preset electrical function, passive resistors and supply rails are inherent to integrated circuits].
5. The IC according to claim 2, wherein the supply-path circuit comprises a keeper circuit [paragraph 0023 the input terminal cannot be floating, a CMOS circuit].
6. The IC according to claim 1, wherein the BFEs are geometrically distributed across the IC so that a maximum distance between any functional node and a nearest BFE is not larger than a predefined maximum FIB-distance [geometric distribution so that a maximum distance is not larger than a predefined maximum is inherent to integrated circuits].
7. The IC according to claim 1, wherein at least some of the metal pads of the BFEs are disposed in a Metal-1 layer of the IC [terminal pad 231].
8. The IC according to claim 1, wherein at least some of the metal pads of the BFEs are disposed in a Top Metal layer of the IC [terminal pads 234 and 254].
9. The IC according to claim 1, wherein the routing circuitry is configured to route the selected BFEs to one or more external connections of the IC [inherent for an integrated circuit and FIB process].
13. The IC according to claim 1, further comprising a FIB-connection pad [paragraph 0007 When FIB debug is performed the signal should be transferred to the top layer, terminal pads 234 and 254], which is (i) connected to a functional node of the functional circuitry [paragraph 0025 to enable the cell 220, coupled to the previous-stage circuit (not shown) and a next-stage circuit (not shown)], (ii) fabricated in a same layer as a metal pad of a given BFE [M4], and (iii) configured to be connected using FIB editing to the metal pad of the given BFE [paragraph 0024 exemplary FIB debug for the integrated circuit, an ion beam is used].
14. The IC according to claim 1, wherein, in a given BFE, the metal pad at least partially overlaps the supply-path circuit [paragraph 0023 system power voltage VCC usually disposed in M1, terminal pads 232-234 and 254 overlap; also inherent that power rails runs throughout an integrated circuit].
15. A method for producing an Integrated Circuit (IC) designed for debugging by Focused Ion Beam (FIB) editing [paragraph 0002 an integrated circuit adapted for FIB debug], the method comprising:
fabricating in the IC functional circuitry comprising functional nodes [inherent that an integrated circuit is fabricated, paragraph 0024 previous stage circuit (not shown) and a next stage circuit (not shown); paragraph 0005 standard cells, paragraph 0025 photo mask];
fabricating in the IC a network of Basic FIB elements (BFEs) [inherent that an integrated circuit is fabricated, paragraph 0022 spare cell 220, only one element is depicted for simplicity of understanding the invention, it is inherent that a network is present in an integrated circuit, paragraph 0025 photo mask], each comprising a respective metal pad configured to be connected to one of the functional nodes using FIB editing [paragraph 0023 any of terminal pads 231-234, paragraph 0024 terminal pad 254 or 234]; and
fabricating in the IC routing circuitry, configured to route one or more selected BFEs for analysis [inherent that an integrated circuit is fabricated, paragraph 0022 coupled by the via structure, paragraph 0023 the via structure means a structure to electrically connect, Because the spare cell is prepared for debug, paragraph 0024 exemplary FIB debug for the integrated circuit, paragraph 0025 photo mask].
16. A method for debugging an Integrated Circuit (IC) by Focused Ion Beam (FIB) editing [paragraph 0002 an integrated circuit adapted for FIB debug], the method comprising:
operating an IC that comprises (i) functional circuitry comprising functional nodes [paragraph 0024 previous stage circuit (not shown) and a next stage circuit (not shown); paragraph 0005 standard cells], (ii) a network of Basic FIB elements (BFEs) [paragraph 0022 spare cell 220, only one element is depicted for simplicity of understanding the invention, it is inherent that a network is present in an integrated circuit] each comprising a respective metal pad configured to be connected to one of the functional nodes using FIB editing [paragraph 0023 any of terminal pads 231-234, paragraph 0024 terminal pad 254 or 234], and (iii) routing circuitry configured to route one or more selected BFEs for analysis [paragraph 0022 coupled by the via structure, paragraph 0023 the via structure means a structure to electrically connect, Because the spare cell is prepared for debug, paragraph 0024 exemplary FIB debug for the integrated circuit];
applying FIB editing to at least a selected functional node among the functional nodes and to at least a selected BEE among the BFEs [paragraph 0025 to enable the cell 220, coupled to the previous-stage circuit (not shown) and a next-stage circuit (not shown)]; and
monitoring a signal on the selected functional node using the routing circuitry [inherent to debugging].
17. The method according to claim 16, wherein applying the FIB editing comprises connecting the selected functional node to the selected BFE using FIB deposition [paragraph 0024 the terminal pads are coupled to a previous-stage circuit (not shown) and a next-stage circuit (not shown), paragraph 0025 to enable the cell 220, coupled to the previous-stage circuit (not shown) and a next-stage circuit (not shown), deposition is inherent to FIB processing].
18. The method according to claim 17, wherein applying the FIB editing further comprises disconnecting a supply-path circuit from the metal pad of the selected BFE using FIB etching [paragraph 0024 ion beam is used for disconnecting the input terminal of the spare cell and the system power VCC, etching is inherent to FIB processing].
19. The method according to claim 17, wherein applying the FIB editing comprises disconnecting a transistor of a supply-path circuit of the selected BFE using FIB etching [paragraph 0022 logic function, paragraph 0024 ion beam is used for disconnecting the input terminal of the spare cell and the system power VCC, etching is inherent to FIB processing].
Claims 1-9 and 13-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Geiger et al. [US 2023/0197537 A1].
As per claim 1, an Integrated Circuit (IC) designed for debugging by Focused Ion Beam (FIB) editing, the IC comprising:
functional circuitry comprising functional nodes [paragraph 0015 plurality of transistors 133, paragraph 0059 plurality of transistors (not shown)];
a network of Basic FIB elements (BFEs) [paragraph 0015 test structure 120, paragraph 0032 using a plurality of test pads and achievable pitch may define an area is interpreted as a network, paragraph 0061 test structure 220], each comprising a respective metal pad configured to be connected to one of the functional nodes using FIB editing [paragraph 0015 backside test pad 150, paragraph 0042 individually connecting the test pads to the test structure, paragraph 0061 test pads can be distributed]; and
routing circuitry, configured to route one or more selected BFEs for analysis [paragraph 0016 electrically conductive connection 140 may comprise the signal line, paragraph 0070 post silicon debug, FIB].
2. The IC according to claim 1, wherein each BFE among one or more of the BFEs further comprises a respective supply-path circuit configured to provide a galvanic path between the BFE and a supply input of the IC [paragraphs 0024, 0080, 0087].
3. The IC according to claim 2, wherein the supply-path circuit comprises a passive resistor that is coupled to a supply rail of the IC [paragraphs 0024, 0030 resistor].
4. The IC according to claim 2, wherein the supply-path circuit comprises an active resistance path to a supply rail of the IC [paragraphs 0024, 0080].
5. The IC according to claim 2, wherein the supply-path circuit comprises a keeper circuit [paragraphs 0024, 0069 short-loop or full-loop, 0080].
6. The IC according to claim 1, wherein the BFEs are geometrically distributed across the IC so that a maximum distance between any functional node and a nearest BFE is not larger than a predefined maximum FIB-distance [paragraphs 0032 and 0038 area is defined by achievable minimum pitch, paragraph 0025 electrically conductive connection have a maximal width and paragraph 0029 test pad have a maximal dimension, it is interpreted that these features provide geometric distribution so that a maximum distance is not larger than a predefined maximum].
7. The IC according to claim 1, wherein at least some of the metal pads of the BFEs are disposed in a Metal-1 layer of the IC [paragraph 0029 lower metal level, paragraph 0080 lower metal layers].
8. The IC according to claim 1, wherein at least some of the metal pads of the BFEs are disposed in a Top Metal layer of the IC [paragraph 0067 front side test pad 252/252’ can be placed in the highest metal layer].
9. The IC according to claim 1, wherein the routing circuitry is configured to route the selected BFEs to one or more external connections of the IC [paragraph 0090 the example ICs route to one or more external connections].
13. The IC according to claim 1, further comprising a FIB-connection pad [paragraph 0070 for post silicon debug, FIB], which is (i) connected to a functional node of the functional circuitry [paragraph 0070 FIB requires very accurate navigation to the signal lines], (ii) fabricated in a same layer as a metal pad of a given BFE [paragraph 0071 four-terminal sensing, pads 252 and 252’ depicted in same layer in FIGS. 3-4, pads 150 and 150’ depicted in same layer in FIGS. 3-4], and (iii) configured to be connected using FIB editing to the metal pad of the given BFE [paragraph 0070 FIB edits].
14. The IC according to claim 1, wherein, in a given BFE, the metal pad at least partially overlaps the supply-path circuit [FIGS. 1-4 depict overlaps, paragraph 0084].
15. A method for producing an Integrated Circuit (IC) designed for debugging by Focused Ion Beam (FIB) editing, the method comprising:
fabricating in [0090 during the manufacturing] the IC functional circuitry comprising functional nodes [paragraph 0015 plurality of transistors 133, paragraph 0059 plurality of transistors (not shown)];
fabricating in [0090 during the manufacturing] the IC a network of Basic FIB elements (BFEs) [paragraph 0015 test structure 120, paragraph 0032 using a plurality of test pads and achievable pitch may define an area is interpreted as a network, paragraph 0061 test structure 220], each comprising a respective metal pad configured to be connected to one of the functional nodes using FIB editing [paragraph 0015 backside test pad 150, paragraph 0042 individually connecting the test pads to the test structure, paragraph 0061 test pads can be distributed]; and
fabricating in [0090 during the manufacturing] the IC routing circuitry, configured to route one or more selected BFEs for analysis [paragraph 0016 electrically conductive connection 140 may comprise the signal line, paragraph 0070 post silicon debug, FIB].
16. A method for debugging an Integrated Circuit (IC) by Focused Ion Beam (FIB) editing, the method comprising:
operating an IC that comprises (i) functional circuitry comprising functional nodes [paragraph 0015 plurality of transistors 133, paragraph 0059 plurality of transistors (not shown)], (ii) a network of Basic FIB elements (BFEs) [paragraph 0015 test structure 120, paragraph 0032 using a plurality of test pads and achievable pitch may define an area is interpreted as a network, paragraph 0061 test structure 220] each comprising a respective metal pad configured to be connected to one of the functional nodes using FIB editing [paragraph 0015 backside test pad 150, paragraph 0042 individually connecting the test pads to the test structure, paragraph 0061 test pads can be distributed], and (iii) routing circuitry configured to route one or more selected BFEs for analysis [paragraph 0016 electrically conductive connection 140 may comprise the signal line, paragraph 0070 post silicon debug, FIB];
applying FIB editing to at least a selected functional node among the functional nodes and to at least a selected BEE among the BFEs [paragraph 0070 quick access to critical signals for post silicon debug, FIB edits]; and
monitoring a signal on the selected functional node using the routing circuitry [paragraph 0070 FIB requires very accurate navigation to the signal lines].
17. The method according to claim 16, wherein applying the FIB editing comprises connecting the selected functional node to the selected BFE using FIB deposition [deposition is inherent to FIB].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai [US 2005/0224950 A1] or Geiger et al. [US 2023/0197537 A1] in view of Best et al. [US 2021/0035924 A1].
As per claim 10, Tsai and Geiger et al. teach the features from which the claim depends. However, neither Tsai nor Geiger et al. teach further comprising an on-chip analysis circuit configured to perform at least part of the analysis, wherein the routing circuitry is configured to route one or more of the selected BFEs to the on-chip analysis circuit. Best et al. teach a security mesh as an on-chip analysis circuit [FIGS. 1A-B, 2A-B, 3, paragraph 0028]. The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because combining on-chip analysis with the routing circuitry of either Tsai or Geiger et al. would thwart an adversary.
Claim 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai [US 2005/0224950 A1] or Geiger et al. [US 2023/0197537 A1] in view of Sugasawara [US 5,936,876].
Tsai and Geiger et al. teach the features from which the claims depend. However, neither Tsai nor Geiger et al. teach wherein the routing circuitry comprises one or more multiplexers, wherein the routing circuitry comprises a chain of buffers. Sugasawara teaches an IC designed for debugging by FIB editing [column 6, line 55-column 7, line 18], including wherein the routing circuitry comprises one or more multiplexers [column 5, line 48-column 6, line 8], wherein the routing circuitry comprises a chain of buffers [column 4, lines 46-55]. The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because combining one or more multiplexers, a chain of buffers, with the routing circuitry of either Tsai or Geiger et al. would isolate the internal probe pads so as to avoid affecting normal operation of the chip, would provide for signal buffering and ESD protection.
Conclusion
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/LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851