DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/26/2026 has been entered.
Claims’ Status & Response to Amendment
Claims 1-20 are currently pending and being examined. Claims 1-3, 6-9, 12-16, and 19-20 have been amended. No claims have been cancelled or newly added.
The objections of the last Office Action (filed 11/25/2025) of Claims 2-3, 6-7, 8-9, 12-13, 15-16, and 19-20 are withdrawn due to the underlying issues having been fixed by amendment.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6, 14, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al (US 2023/0378298 A1, hereafter Li).
Re Claim 1, Li discloses a semiconductor device (FIG. 13; [0016]-[0040]) comprising:
a plurality of nanosheets stacks (208; [0017]);
an upper portion of a source drain epitaxy (234, 236; [0030]) adjacent to a first group of semiconductor channel layers (208, left stack in FIG. 13, hereafter just 208, left stack; [0032]) and a second group of semiconductor channel layers (208, right stack in FIG. 13, hereafter just 208, right stack; [0032]) of adjacent nanosheet stacks (208) of the plurality of nanosheets stacks (208) on a substrate (202; [0032]), wherein the first and second group of semiconductor layers (208, left/right stacks) each include a plurality of channel layers (208; [0032]), wherein the upper portion of the source drain epitaxy (234, 236) forms a laterally continuous element (236; [0032]) between the first group of semiconductor channel layers (208, left stack) and the second group of semiconductor channel layers (208, right stack; [0032], 236 is laterally continuous “between” the two groups); and
a lower portion of the source drain epitaxy (232; [0029]) below the upper portion of the source drain epitaxy (234, 236; [0030]), wherein a second width of the lower portion of the source drain epitaxy (232, at its widest; [0029]) is greater than a first width of the upper portion of the source drain epitaxy (234, 236, at their widest; [0030]), wherein a portion of the lower portion of the source drain epitaxy (232) is vertically aligned with an inner spacer (230; [0029]) of each of the adjacent nanosheet stacks of the plurality of nanosheet stacks (208; [0029]).
Re Claim 6, Li discloses the device according to Claim 1, while further disclosing wherein each of the plurality of nanosheets stacks (208) comprises a set of semiconductor channel layers (208) vertically aligned and stacked one on top of another ([0020]), the set of semiconductor channel layers (208) separated from each other by a gate stack material (242; [0037]) surrounding the set of semiconductor channel layers (208; [0037]).
Re Claim 14, Li discloses a method (FIGS. 3-13; [0016]-[0040]) comprising:
forming a plurality of nanosheets stacks (208; [0017]);
forming an upper portion of a source drain epitaxy (234, 236; [0030]) adjacent to a first group of semiconductor channel layers (208, left stack in FIG. 13, hereafter just 208, left stack; [0032]) and a second group of semiconductor channel layers (208, right stack in FIG. 13, hereafter just 208, right stack; [0032]) of adjacent nanosheet stacks (208) of the plurality of nanosheets stacks (208) on a substrate (202; [0032]), wherein the first and second group of semiconductor layers (208, left/right stacks) each include a plurality of channel layers (208; [0032]), wherein the upper portion of the source drain epitaxy (234, 236) forms a laterally continuous element (236; [0032]) between the first group of semiconductor channel layers (208, left stack) and the second group of semiconductor channel layers (208, right stack; [0032], 236 is laterally continuous “between” the two groups); and
forming a lower portion of the source drain epitaxy (232; [0029]) below the upper portion of the source drain epitaxy (234, 236; [0030]), wherein a second width of the lower portion of the source drain epitaxy (232, at its widest; [0029]) is greater than a first width of the upper portion of the source drain epitaxy (234, 236, at their widest; [0030]), wherein a portion of the lower portion of the source drain epitaxy (232) is vertically aligned with an inner spacer (230; [0029]) of each of the adjacent nanosheet stacks of the plurality of nanosheet stacks (208; [0029]).
Re Claim 19, Li discloses the device according to Claim 14, while further disclosing wherein each of the plurality of nanosheets stacks (208) comprises a set of semiconductor channel layers (208) vertically aligned and stacked one on top of another ([0020]), the set of semiconductor channel layers (208) separated from each other by a gate stack material (242; [0037]) surrounding the set of semiconductor channel layers (208; [0037]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Li, as applied to Claim 1, in view of Su (US 2022/0384589 A1, of record, hereafter Su).
Re Claim 2, Li discloses the device according to Claim 1, but does not explicitly disclose the device further comprises:
a dielectric fill layer below the plurality of nanosheet stacks (208); and
a dielectric encapsulation liner between the dielectric fill layer and the lower portion of the source drain epitaxy (232).
However, Su teaches a semiconductor device (FIG. 2; [0022]-[0028]), comprising:
a dielectric fill layer (126; [0027]) below the plurality of nanosheet stacks (102; [0022]); and
a dielectric encapsulation liner (127; [0027]) between the dielectric fill layer (126) and the lower portion of the source drain epitaxy (107; [0046], not shown explicitly in FIG. 2, but 107 would be formed between 106 and 120).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 1 with the limitations taught by Su to include the dielectric fill layer (Su: 126) and dielectric encapsulation liner (Su: 127) to help improve electrical isolation of the gate structure as taught by Su ([0027]).
Re Claim 3, Li and Su teach the device according to Claim 2, while Su further teaches the device comprises:
the dielectric encapsulation liner (127) between the dielectric fill layer (126) and the lowest channel layer (102; [0022]) of one of the plurality of nanosheet stacks (102; [0022]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 2 with the limitations taught by Su to include the dielectric fill layer (Su: 126) and dielectric encapsulation liner (Su: 127) to help improve electrical isolation of the gate structure as taught by Su ([0027]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Li and Su, as applied to Claim 2, further in view of Yao et al (US 2020/0328121 A1, of record, hereafter Yao).
Re Claim 4, Li and Su teach the device according to Claim 2, but they do not explicitly disclose the device further comprises:
an air gap in the dielectric fill layer (Su: 126) between adjacent lower portions of the source drain epitaxy (Li: 232).
However, Yao teaches a semiconductor device (FIG. 10; [0068]-[0071]) comprising:
an air gap (62; [0065]) in the dielectric fill layer (60; [0065]) between adjacent lower portions of the source drain epitaxy (18; [0069]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 2 with the limitations taught by Yao to introduce an air gap (Yao: 62) into the dielectric fill (Su: 126) between adjacent source and drains (Li: 232) to reduce parasitic capacitance as taught by Yao ([0065]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Li as applied to Claim 1 in view of Liu et al (US 2021/0376071 A1, of record, hereafter Liu).
Re Claim 7, Li discloses the device according to Claim 1, but does not explicitly disclose the device further comprises:
a gate cut dielectric between a second set of adjacent nanosheet stacks of the plurality of nanosheet stacks (Li: 208).
However, Liu teaches a semiconductor device (FIG. 19C-3; [0042]), comprising:
a gate cut dielectric (229; [0042]) between a second set of adjacent nanosheet stacks (215; [0041]) of the plurality of nanosheets stacks (215; [0041]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 1 with the limitations taught by Liu to include a gate cut dielectric (Liu: 229) between adjacent nanosheet stacks (Li: 208) to effectively create a plurality of separated gate segments as taught by Liu ([0042]).
Claims 8-9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Su.
Re Claim 8, Li discloses a semiconductor device (FIG. 13; [0016]-[0040]) comprising:
a plurality of nanosheets stacks (208; [0017]);
an upper portion of a source drain epitaxy (234, 236; [0030]) adjacent to a first group of semiconductor channel layers (208, left stack in FIG. 13, hereafter just 208, left stack; [0032]) and a second group of semiconductor channel layers (208, right stack in FIG. 13, hereafter just 208, right stack; [0032]) of adjacent nanosheet stacks (208) of the plurality of nanosheets stacks (208) on a substrate (202; [0032]), wherein the first and second group of semiconductor layers (208, left/right stacks) each include a plurality of channel layers (208; [0032]), wherein the upper portion of the source drain epitaxy (234, 236) forms a laterally continuous element (236; [0032]) between the first group of semiconductor channel layers (208, left stack) and the second group of semiconductor channel layers (208, right stack; [0032], 236 is laterally continuous “between” the two groups); and
a lower portion of the source drain epitaxy (232; [0029]) below the upper portion of the source drain epitaxy (234, 236; [0030]), wherein a second width of the lower portion of the source drain epitaxy (232, at its widest; [0029]) is greater than a first width of the upper portion of the source drain epitaxy (234, 236, at their widest; [0030]), wherein a portion of the lower portion of the source drain epitaxy (232) is vertically aligned with an inner spacer (230; [0029]) of each of the adjacent nanosheet stacks of the plurality of nanosheet stacks (208; [0029]).
Li does not explicitly disclose the device further comprises:
a dielectric fill layer below the plurality of nanosheet stacks (208); and
a dielectric encapsulation liner between the dielectric fill layer and the lower portion of the source drain epitaxy (232).
However, Su teaches a semiconductor device (FIG. 2; [0022]-[0028]), comprising:
a dielectric fill layer (126; [0027]) below the plurality of nanosheet stacks (102; [0022]); and
a dielectric encapsulation liner (127; [0027]) between the dielectric fill layer (126) and the lower portion of the source drain epitaxy (107; [0046], not shown explicitly in FIG. 2, but 107 would be formed between 106 and 120).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Li with the limitations taught by Su to include the dielectric fill layer (Su: 126) and dielectric encapsulation liner (Su: 127) to help improve electrical isolation of the gate structure as taught by Su ([0027]).
Re Claim 9, Li and Su teach the device according to Claim 8, while Su further teaches the device comprises:
the dielectric encapsulation liner (127) between the dielectric fill layer (126) and the lowest channel layer (102; [0022]) of one of the plurality of nanosheet stacks (102; [0022]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 8 with the limitations taught by Su to include the dielectric fill layer (Su: 126) and dielectric encapsulation liner (Su: 127) to help improve electrical isolation of the gate structure as taught by Su ([0027]).
Re Claim 12, Li and Su teach the device according to Claim 8, while Li further discloses wherein each of the plurality of nanosheets stacks (208) comprises a set of semiconductor channel layers (208) vertically aligned and stacked one on top of another ([0020]), the set of semiconductor channel layers (208) separated from each other by a gate stack material (242; [0037]) surrounding the set of semiconductor channel layers (208; [0037]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Li and Su, as applied to Claim 8, further in view of Yao.
Re Claim 10, Li and Su teach the device according to Claim 8, but they do not explicitly disclose the device further comprises:
an air gap in the dielectric fill layer (Su: 126) between adjacent lower portions of the source drain epitaxy (Li: 232).
However, Yao teaches a semiconductor device (FIG. 10; [0068]-[0071]) comprising:
an air gap (62; [0065]) in the dielectric fill layer (60; [0065]) between adjacent lower portions of the source drain epitaxy (18; [0069]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 8 with the limitations taught by Yao to introduce an air gap (Yao: 62) into the dielectric fill (Su: 126) between adjacent source and drains (Li: 232) to reduce parasitic capacitance as taught by Yao ([0065]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Li and Su, as applied to Claim 8, further in view of Liu.
Re Claim 13, Li and Su teach the device according to Claim 8, but they do not explicitly disclose the device further comprises:
a gate cut dielectric between a second set of adjacent nanosheet stacks of the plurality of nanosheet stacks (Li: 208).
However, Liu teaches a semiconductor device (FIG. 19C-3; [0042]), comprising:
a gate cut dielectric (229; [0042]) between a second set of adjacent nanosheet stacks (215; [0041]) of the plurality of nanosheets stacks (215; [0041]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 8 with the limitations taught by Liu to include a gate cut dielectric (Liu: 229) between adjacent nanosheet stacks (Li: 208) to effectively create a plurality of separated gate segments as taught by Liu ([0042]).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Li, as applied to Claim 14, in view of Su.
Re Claim 15, Li discloses the method according to Claim 14, but does not explicitly disclose the method further comprises:
forming a dielectric fill layer below a lowest semiconductor channel layer of one of the plurality of nanosheet stacks (208); and
forming a dielectric encapsulation liner between the dielectric fill layer and the lower portion of the source drain epitaxy (232).
However, Su teaches a method (FIG. 2; [0022]-[0028]), comprising:
forming a dielectric fill layer (126; [0027]) below a lowest semiconductor channel layer (102) of one of the plurality of nanosheet stacks (102; [0022]); and
forming a dielectric encapsulation liner (127; [0027]) between the dielectric fill layer (126) and the lower portion of the source drain epitaxy (107; [0046], not shown explicitly in FIG. 2, but 107 would be formed between 106 and 120).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 14 with the limitations taught by Su to include the dielectric fill layer (Su: 126) and dielectric encapsulation liner (Su: 127) to help improve electrical isolation of the gate structure as taught by Su ([0027]).
Re Claim 16, Li and Su teach the method according to Claim 15, while Su further teaches the method comprises:
forming the dielectric encapsulation liner (127) between the dielectric fill layer (126) and the lowest channel layer (102; [0022]) of one of the plurality of nanosheet stacks (102; [0022]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 15 with the limitations taught by Su to include the dielectric fill layer (Su: 126) and dielectric encapsulation liner (Su: 127) to help improve electrical isolation of the gate structure as taught by Su ([0027]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Li and Su, as applied to Claim 15, further in view of Yao.
Re Claim 17, Li and Su teach the method according to Claim 15, but they do not explicitly disclose the method further comprises:
forming an air gap in the dielectric fill layer (Su: 126) between adjacent lower portions of the source drain epitaxy (Li: 232).
However, Yao teaches a method (FIG. 10; [0068]-[0071]) comprising:
forming an air gap (62; [0065]) in the dielectric fill layer (60; [0065]) between adjacent lower portions of the source drain epitaxy (18; [0069]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 15 with the limitations taught by Yao to introduce an air gap (Yao: 62) into the dielectric fill (Su: 126) between adjacent source and drains (Li: 232) to reduce parasitic capacitance as taught by Yao ([0065]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Li, as applied to Claim 14, in view of Liu.
Re Claim 20, Li discloses the method according to Claim 14, but does not explicitly disclose the method further comprises:
forming a gate cut dielectric between a second set of adjacent nanosheet stacks of the plurality of nanosheet stacks (Li: 208).
However, Liu teaches a method (FIG. 19C-3; [0042]), comprising:
forming a gate cut dielectric (229; [0042]) between a second set of adjacent nanosheet stacks (215; [0041]) of the plurality of nanosheets stacks (215; [0041]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 14 with the limitations taught by Liu to include a gate cut dielectric (Liu: 229) between adjacent nanosheet stacks (Li: 208) to effectively create a plurality of separated gate segments as taught by Liu ([0042]).
Allowable Subject Matter
Claims 5, 11, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 5, the prior art cannot anticipate, or render obvious, the limitations of: the lower portion of the source drain epitaxy comprises a volume concentration of free electrical carriers equal to or more than 7e20 cm-3, in combination with the additionally claimed features of Claim 5.
Re Claim 11, the prior art cannot anticipate, or render obvious, the limitations of: the lower portion of the source drain epitaxy comprises a volume concentration of free electrical carriers equal to or more than 7e20 cm-3, in combination with the additionally claimed features of Claim 11.
Re Claim 18, the prior art cannot anticipate, or render obvious, the limitations of: the lower portion of the source drain epitaxy comprises a volume concentration of free electrical carriers equal to or more than 7e20 cm-3, in combination with the additionally claimed features of Claim 18.
Response to Arguments
Applicant’s arguments, see Remarks pg. 2, para. 4 to pg. 3, para. 2, filed 1/26/2026, with respect to the rejection(s) of Claim 1 and 14 under 35 U.S.C. 102(a)(1) and Claim 8 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Li under 35 U.S.C. 102(a)(2) for Claims 1 and 14 and in view of Li and Su under 35 U.S.C. 103 for Claim 8. Applicant’s arguments have been considered in light of the new rejections but are moot because the new ground(s) of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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