Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 7-9 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pat. Pub. 2022/0285268).
Regarding claim 1, Lee teaches a semiconductor structure comprising:
First metal lines embedded in a first dielectric layer [fig. 5, first dielectric 104, first metal lines 106];
Second metal lines embedded in a second dielectric layer, wherein the second metal lines are arranged above the first metal lines [fig. 5, second dielectric 126, second metal lines 130];
A top via extending between one of the first metal lines and one of the second metal lines wherein a second vertical sidewall of the top via is substantially flush with a vertical sidewall of the one of the second metal lines [fig. 5, 114 between 130 and 106, a second vertical sidewall of 114 is flush with a vertical sidewall of 130]; and
At least one air gap located adjacent to the top via between the first metal lines and the second metal lines [fig. 5, air gap 136 adjacent 114 and between the layers containing 130 and 106].
Lee fails to show a first vertical sidewall of the top via is substantially flush with a vertical sidewall of the first metal line in the same embodiment that shows both a first and second metal lines along with the top vias. However, a different embodiment of Liao shows the top via vertically aligned with the first metal line including vertical sidewalls [fig. 1h, sidewalls of 114 aligned with sidewalls of 106].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of an additional embodiment of Lee into the method of Liao by having a first vertical sidewall of the top via substantially flush with a vertical sidewall of the one of the first metal lines and a second vertical sidewall of the top via is substantially flush with a vertical sidewall of the one of the second metal lines . The ordinary artisan would have been motivated to modify Lee in the manner set forth above for at least the purpose of utilizing a formation that yields precisely aligned openings and interconnect structures preventing any damage from etching [paragraph [0025]].
Regarding claim 2, Lee discloses the semiconductor structure according to claim 1, further comprising:
A dielectric liner surrounding sides and a bottom of the at least one air gap [fig. 5, dielectric 122].
Regarding claim 7, Lee teaches the semiconductor structure according to claim 1, wherein the first meal lines and the second metal lines comprise ruthenium [paragraphs [0015 and 0043] 106 and 130 can be Ru].
Regarding claim 8, Lee discloses a semiconductor structure comprising:
first metal lines embedded in a first dielectric layer [fig. 5, first dielectric 104, first metal lines 106];
second metal lines embedded in a second dielectric layer, wherein the second metal lines are arranged above the first metal lines [fig. 5, second dielectric 126, second metal lines 130 above 106];
a top via extending between one of the first metal lines and one of the second metal lines [fig. 5, 114]; and
at least one air gap located adjacent to the top via between the first metal lines and the second metal lines, wherein the at least one air gap is in the same level as the top via wherein the at least one air gap is entirely above the first metal lines and entirely below the second metal lines [fig. 5, air gap 132 entirely above 106 and entirely below 130].
Lee fails to show the top via is self-aligned to the one of the first metal lines. However, a different embodiment of Liao shows the top via vertically aligned with the first metal line including vertical sidewalls making it self-aligned [fig. 1h, sidewalls of 114 aligned with sidewalls of 106].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of an additional embodiment of Lee into the method of Liao by having a first vertical sidewall of the top via substantially flush with a vertical sidewall of the one of the first metal lines and a second vertical sidewall of the top via is substantially flush with a vertical sidewall of the one of the second metal lines making it self-aligned. The ordinary artisan would have been motivated to modify Lee in the manner set forth above for at least the purpose of utilizing a formation that yields precisely aligned openings and interconnect structures preventing any damage from etching [paragraph [0025]].
Regarding claim 9, Lee discloses the semiconductor structure according to claim 8, further comprising:
A dielectric liner surrounding sides and a bottom of the at least one air gap [fig. 5, dielectric 122].
Regarding claim 14, Lee teaches the semiconductor structure according to claim 8, wherein the first meal lines and the second metal lines comprise ruthenium [paragraphs [0015 and 0043] 106 and 130 can be Ru].
Allowable Subject Matter
Claims 15-25 are allowed.
Claims 3-6, 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a top via extending between one of the first metal lines and one of the second metal lines, wherein the top via is self-aligned to one of the first metal lines and at least one air gap located entirely above the first metal lines and entirely below the second metal lines, wherein the at least one air gap is vertically aligned with another one of the first metal lines.
Regarding claim 22, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a top via extending between one of the first metal lines and one of the second metal lines, wherein a first vertical sidewall of the top via is substantially flush with a vertical sidewall of the one of the first metal lines and a second vertical sidewall of the top via is substantially flush with a vertical sidewall of the one of the second metal lines and masks above and directly contacting topmost surfaces of the first metal lines except where the first metal lines are directly beneath the second metal lines, wherein bottom most surfaces of the masks are substantially flush with a bottom most surface of the top via.
Regarding claim 24, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a top via extending between one of the first metal lines and one of the second metal lines, wherein a first vertical sidewall of the top via is substantially flush with a vertical sidewall of the one of the first metal lines and a second vertical sidewall of the top via is substantially flush with a vertical sidewall of the one of the second metal lines, dielectric plugs located in the same level as the top via and directly above all of the first metal lines except where the top via is positioned and at least one air gap located within at least one of the dielectric plugs separating it from both the first dielectric layer and the second dielectric layer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-24 have been considered but are moot in view of the new grounds of rejection applied above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm.
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/JOHN M PARKER/ Primary Examiner, Art Unit 2899
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