Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 8, 9, 11, 15, 16, 18, and 22 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Seidel et al. (US Pat. Pub. 2010/0301489).
Regarding claim 1, Seidel teaches a semiconductor structure comprising:
first metal lines embedded in a first dielectric layer [fig. 1p, metal lines 132, first dielectric 131];
second metal lines embedded in a second dielectric layer, wherein the second metal lines are arranged above the first metal lines [fig. 1p, second metal lines 161a above 132, in dielectric 144, paragraph [0043] talks of forming vias (more than one) in layer 144, therefore even though a single 161a is shown, there are multiple]
a top via extending between one of the first metal lines and one of the second metal lines, wherein the top via is self-aligned to the one of the first metal lines [fig. 1p, 142 between 161a and 132, aligned to 132]; and
at least one air gap located adjacent to the top via between the first metal lines and the second metal lines [fig. 1p, air gaps 144a are adjacent 142, located in a layer between 161a and 132].
Regarding claim 2, Seidel discloses the semiconductor structure according to claim 1, further comprising:
A dielectric liner surrounding sides and a bottom of the at least one air gap [fig. 1p, 144s].
Regarding claim 4, Seidel teaches the semiconductor structure according to claim 1, further comprising:
masks above and directly contacting topmost surfaces of the first metal lines except where the first metal lines are directly beneath the second metal lines, wherein bottom most surfaces of the masks are substantially flush with a bottom most surface of the top via [fig. 1p, layer 141 can be interpreted as masks, directly contacting the topmost surfaces of 132 except where the top via and second metal lines are present].
Regarding claim 8, Seidel discloses a semiconductor structure comprising:
first metal lines embedded in a first dielectric layer [fig. 1p, metal lines 132, first dielectric 131];
second metal lines embedded in a second dielectric layer, wherein the second metal lines are arranged above the first metal lines [fig. 1p, second metal lines 161a above 132, in dielectric 144, paragraph [0043] talks of forming vias (more than one) in layer 144, therefore even though a single 161a is shown, there are multiple];
a top via extending between one of the first metal lines and one of the second metal lines, wherein the top via is self-aligned to the one of the first metal lines [fig. 1p, 142 between 161a and 132, aligned to 132,]; and
at least one air gap located adjacent to the top via between the first metal lines and the second metal lines, wherein the at least one air gap is in the same level as the top via [fig. 1p, air gaps 144a are adjacent 142, located in a layer between 161a and 132, 142 is at the same level as 144a].
Regarding claim 9, Seidel discloses the semiconductor structure according to claim 8, further comprising:
A dielectric liner surrounding sides and a bottom of the at least one air gap [fig. 1p, 144s].
Regarding claim 11, Seidel teaches the semiconductor structure according to claim 8, further comprising:
masks above and directly contacting topmost surfaces of the first metal lines except where the first metal lines are directly beneath the second metal lines, wherein bottom most surfaces of the masks are substantially flush with a bottom most surface of the top via [fig. 1p, layer 141 can be interpreted as masks, directly contacting the topmost surfaces of 132 except where the top via and second metal lines are present].
Regarding claim 15, Seidel discloses a semiconductor structure comprising:
first metal lines embedded in a first dielectric layer [fig. 1p, metal lines 132, first dielectric 131];
second metal lines embedded in a second dielectric layer, wherein the second metal lines are arranged above the first metal lines [fig. 1p, second metal lines 161a above 132, in dielectric 144, paragraph [0043] talks of forming vias (more than one) in layer 144, therefore even though a single 161a is shown, there are multiple];
a top via extending between one of the first metal lines and one of the second metal lines, wherein the top via is self-aligned to the one of the first metal lines [fig. 1p, 142 between 161a and 132, aligned to 132,]; and
at least one air gap located in the same level as the top via, wherein the at least one air gap is arranged at intersections between the first metal lines and the second metal lines [fig. 1p, air gaps 144a are adjacent 142, located in a layer between 161a and 132, in a top view the air gap would be at an intersection between 161a and 132, fig. 1o shows a slightly misaligned 161a which would also depict 144a at an intersection between 161a and 132 in a top view, 142 is at the same level as 144a].
Regarding claim 16, Seidel discloses the semiconductor structure according to claim 15, further comprising:
A dielectric liner surrounding sides and a bottom of the at least one air gap [fig. 1p, 144s].
Regarding claim 18, Seidel teaches the semiconductor structure according to claim 15, further comprising:
masks above and directly contacting topmost surfaces of the first metal lines except where the first metal lines are directly beneath the second metal lines, wherein bottom most surfaces of the masks are substantially flush with a bottom most surface of the top via [fig. 1p, layer 141 can be interpreted as masks, directly contacting the topmost surfaces of 132 except where the top via and second metal lines are present].
Regarding claim 22, Seidel discloses a semiconductor structure comprising:
first metal lines embedded in a first dielectric layer [fig. 1p, metal lines 132, first dielectric 131];
second metal lines embedded in a second dielectric layer, wherein the second metal lines are arranged above the first metal lines [fig. 1p, second metal lines 161a above 132, in dielectric 144, paragraph [0043] talks of forming vias (more than one) in layer 144, therefore even though a single 161a is shown, there are multiple];
a top via extending between one of the first metal lines and one of the second metal lines, wherein the top via is self-aligned to the one of the first metal lines [fig. 1p, 142 between 161a and 132, aligned to 132,]; and
at least one air gap located in the same level as the top via, wherein the at least one air gap is arranged at intersections between the first metal lines and the second metal lines [fig. 1p, air gaps 144a are adjacent 142, located in a layer between 161a and 132, in a top view the air gap would be at an intersection between 161a and 132, fig. 1o shows a slightly misaligned 161a which would also depict 144a at an intersection between 161a and 132 in a top view, 142 is at the same level as 144a].
A dielectric liner surrounding sides and a bottom of the at least one air gap [fig. 1p, 144s].
masks above and directly contacting topmost surfaces of the first metal lines except where the first metal lines are directly beneath the second metal lines, wherein bottom most surfaces of the masks are substantially flush with a bottom most surface of the top via [fig. 1p, layer 141 can be interpreted as masks, directly contacting the topmost surfaces of 132 except where the top via and second metal lines are present].
Claim(s) 1-3, 8-10, 15-17, 24 and 25 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kaneko et al. (US Pat. Pub. 2015/0076708).
Regarding claim 1, Kaneko teaches a semiconductor structure comprising:
first metal lines embedded in a first dielectric layer [fig. 4, metal lines 6, first dielectric 4];
second metal lines embedded in a second dielectric layer, wherein the second metal lines are arranged above the first metal lines [fig. 4, metal lines 13 in second dielectric 11, above first metal lines 6]
a top via extending between one of the first metal lines and one of the second metal lines, wherein the top via is self-aligned to the one of the first metal lines [fig. 4, top via 9 between 13 and 6, paragraph [0087] teaches 9 is self-aligned with 6a which is part of 6]; and
at least one air gap located adjacent to the top via between the first metal lines and the second metal lines [fig. 4, air gap 15 adjacent 9 between 13 and 6].
Regarding claim 2, Kaneko discloses the semiconductor structure according to claim 1, further comprising:
A dielectric liner surrounding sides and a bottom of the at least one air gap [fig. 4, dielectric 7 surrounds sides and bottom of 15].
Regarding claim 3, Kaneko teaches the semiconductor structure according to claim 2, wherein the dielectric liner directly contacts all topmost surfaces of the first metal lines directly beneath the second metal lines except where the top via is positioned [fig. 4, dielectric 7 contacts top surfaces of 6 except where 9 is present].
Regarding claim 8, Kaneko teaches a semiconductor structure comprising:
first metal lines embedded in a first dielectric layer [fig. 4, metal lines 6, first dielectric 4];
second metal lines embedded in a second dielectric layer, wherein the second metal lines are arranged above the first metal lines [fig. 4, metal lines 13 in second dielectric 11, above first metal lines 6]
a top via extending between one of the first metal lines and one of the second metal lines, wherein the top via is self-aligned to the one of the first metal lines [fig. 4, top via 9 between 13 and 6, paragraph [0087] teaches 9 is self-aligned with 6a which is part of 6]; and
at least one air gap located adjacent to the top via between the first metal lines and the second metal lines, wherein the at least one air gap is in the same level as the top via [fig. 4, air gap 15 adjacent 9 between 13 and 6, 15 is in the same level as 9].
Regarding claim 9, Kaneko discloses the semiconductor structure according to claim 8, further comprising:
A dielectric liner surrounding sides and a bottom of the at least one air gap [fig. 4, dielectric 7 surrounds sides and bottom of 15].
Regarding claim 10, Kaneko teaches the semiconductor structure according to claim 9, wherein the dielectric liner directly contacts all topmost surfaces of the first metal lines directly beneath the second metal lines except where the top via is positioned [fig. 4, dielectric 7 contacts top surfaces of 6 except where 9 is present].
Regarding claim 15, Kaneko teaches a semiconductor structure comprising:
first metal lines embedded in a first dielectric layer [fig. 4, metal lines 6, first dielectric 4];
second metal lines embedded in a second dielectric layer, wherein the second metal lines are arranged above the first metal lines [fig. 4, metal lines 13 in second dielectric 11, above first metal lines 6]
a top via extending between one of the first metal lines and one of the second metal lines, wherein the top via is self-aligned to the one of the first metal lines [fig. 4, top via 9 between 13 and 6, paragraph [0087] teaches 9 is self-aligned with 6a which is part of 6]; and
at least one air gap is located in the same level as the top via, wherein the at least one air gap is arranged at intersections between the first metal lines and the second metal lines [fig. 4, air gap 15 adjacent 9, at intersections between 13 and 6 in a top view, 15 is in the same level as 9].
Regarding claim 16, Kaneko discloses the semiconductor structure according to claim 15, further comprising:
A dielectric liner surrounding sides and a bottom of the at least one air gap [fig. 4, dielectric 7 surrounds sides and bottom of 15].
Regarding claim 17, Kaneko teaches the semiconductor structure according to claim 16, wherein the dielectric liner directly contacts all topmost surfaces of the first metal lines directly beneath the second metal lines except where the top via is positioned [fig. 4, dielectric 7 contacts top surfaces of 6 except where 9 is present].
Regarding claim 24, Kaneko teaches a semiconductor structure comprising:
first metal lines embedded in a first dielectric layer [fig. 4, metal lines 6, first dielectric 4];
second metal lines embedded in a second dielectric layer, wherein the second metal lines are arranged above the first metal lines [fig. 4, metal lines 13 in second dielectric 11, above first metal lines 6];
a top via extending between one of the first metal lines and one of the second metal lines, wherein the top via is self-aligned to the one of the first metal lines [fig. 4, top via 9 between 13 and 6, paragraph [0087] teaches 9 is self-aligned with 6a which is part of 6];
dielectric plugs located in the same level as the top via and directly above all of the first metal lines except where the top via is positioned [fig. 4, dielectric plugs 7 are in the same level as 9 and present above 5 except where 9 is present]; and
at least one air gap located within at least one of the dielectric plugs separating it from both the first dielectric layer and the second dielectric layer [fig. 4, 15 is within dielectric 7 and separated from 11 and 4].
Regarding claim 25, Kaneko discloses the semiconductor structure according to claim 24, wherein each of the dielectric plugs is self-aligned with each of the first metal lines respectively [fig. 8b and 11b show the dielectric 7 is formed to be self-aligned above 6].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7, 14 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seidel as applied to claims 1, 2, 4, 8, 9, 11, 15, 16, 18, and 22 above, and further in view of Liao et al.
Regarding claim 7, Seidel fails to teach the first and second metal lines comprise ruthenium, instead teaching copper.
However, Liao teaches a semiconductor interconnect structure with metal lines (wires) and vias made out of metals including copper or ruthenium among others [fig. 1, paragraphs [0022] and [0024]].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Liao into the method of Seidel by forming the first and second metal lines out of ruthenium. The ordinary artisan would have been motivated to modify Seidel in the manner set forth above for at least the purpose of utilizing known functional metal materials to ensure successful device fabrication. Additionally, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07.
Regarding claim 14, Seidel fails to teach the first and second metal lines comprise ruthenium, instead teaching copper.
However, Liao teaches a semiconductor interconnect structure with metal lines (wires) and vias made out of metals including copper or ruthenium among others [fig. 1, paragraphs [0022] and [0024]].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Liao into the method of Seidel by forming the first and second metal lines out of ruthenium. The ordinary artisan would have been motivated to modify Seidel in the manner set forth above for at least the purpose of utilizing known functional metal materials to ensure successful device fabrication. Additionally, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07.
Regarding claim 21, Seidel fails to teach the first and second metal lines comprise ruthenium, instead teaching copper.
However, Liao teaches a semiconductor interconnect structure with metal lines (wires) and vias made out of metals including copper or ruthenium among others [fig. 1, paragraphs [0022] and [0024]].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Liao into the method of Seidel by forming the first and second metal lines out of ruthenium. The ordinary artisan would have been motivated to modify Seidel in the manner set forth above for at least the purpose of utilizing known functional metal materials to ensure successful device fabrication. Additionally, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07.
Allowable Subject Matter
Claims 5, 6, 12, 13, 19, 20 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JOHN M PARKER/Examiner, Art Unit 2899