DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 06/29/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over LIAW (US 20190287967 A1) in view of Huang et al. (US 20220130765 A1; hereafter Huang).
As of Claim 1: LIAW teaches an integrated circuit (IC) device (¶0023 and note integrated circuit (IC)), comprising: a transistor comprising: a source region, a drain region (¶¶0023,0031,0041 and note that the gate electrodes 130 and 132 extend along an X-direction of the layout 100. The X-direction of the layout 100A can be referred to as the Y-direction of FIG. 1. The gate electrodes 130 and 132 are across first and second active area regions 111 and 121. Example materials of the gate electrodes 130 and 132 include, but are not limited to, polysilicon and metal. Other materials are within the scope of various embodiments. The gate electrodes 130 and 132 and the corresponding first and second active area regions 111 and 121 form one or more transistors in the layout 100A. In the example configuration in FIG. 3, a transistor may be formed by the gate electrode 132 and the first active area region 111. Also, transistor having a gate, a drain, and a source is formed in the first circuit 102. For example, the gate of the transistor is formed by the gate electrode 132. One of the drain or the source (referred to herein as “source/drain” or “S/D”) of the transistor is defined by a region of the first active area region 111 on one side (e.g., the upper side in FIG. 3) of the gate electrode 132. The other source/drain of the transistor may be defined by another region of the first active area region 111 on the opposite side (e.g., the lower side in FIG. 3) of the gate electrode 132.); and an assembly comprising: a first semiconductor region, a second semiconductor region, and a dielectric structure between the first semiconductor region and the second semiconductor region in the first direction (¶¶0037,0046,0049-0051 and note that the semiconductor device 100 further comprises active area regions, gate electrodes, and corresponding spacers over the isolation structure. In the example configuration in FIGS. 4 and 5, the semiconductor device 100 further comprises the first, second, third, fourth active area regions 111, 121, 151, 161, the gate electrodes 132, 172, and corresponding spacers 206, 208, 210, 212 over the corresponding isolation structures 204A and 204B), wherein the dielectric structure is over the gate electrode in a second direction that is perpendicular or substantially perpendicular to the first direction (¶¶0051,0098).
Huang is a similar or analogous system to the claimed invention as evidenced Huang teaches integrated circuit (IC) chips comprise a group III-V semiconductor stack overlying and epitaxially grown on a first silicon substrate and further comprise a high-electron-mobility transistor (HEMT) overlying and formed on the group III-V semiconductor stack would have prompted a predictable variation of LIAW by applying Huang’s known principal of a gate electrode between the source region and the drain region in a first direction (¶¶0040,0048,0050).
In view of the motivations such as source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad thereby further reducing substrate power loss as disclosed in ¶0025 and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of LIAW.
Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
As of Claim 2: LIAW in view of Huang further teaches an additional transistor comprising an additional gate electrode, wherein the additional gate electrode is separated from the gate electrode by an electrical insulator (Huang ¶¶0022,0024,0028 and note that the active semiconductor region 112 is defined by the semiconductor layer 108, and the source/drain electrodes 114 and the gate electrode 116 underlie the active semiconductor region 112. Because source/drain electrodes 114 and the gate electrode 116 underlie the active semiconductor region 112, instead of overlying the active semiconductor region 112, the semiconductor device 102 is said to be “vertically inverted”. The source/drain electrodes 114 are respectively on and electrically coupled to opposite sides of the active semiconductor region 112, and the gate electrode 116 is between the source/drain electrodes 114. ).
As of Claim 3: LIAW in view of Huang further teaches the additional gate electrode is over the gate electrode in the second direction (LIAW ¶¶0022,0025,0031,0041 and note one or more of the gate electrodes 170 and 172 are coupled to other circuitry of the semiconductor device by corresponding gate contacts. For example, gate contacts may be formed on the corresponding gate electrodes 170 and 172 and configured to electrically couple to the corresponding gate electrodes 170 and 172 to other circuitry. Furthermore, at least one of the gate electrodes 170 and 172 has a second gate length L2 along a longitudinal direction of at least one of the second fins 152-158, 162-168 (i.e., the Y-direction of the layout 100A)).
As of Claim 4: LIAW in view of Huang further teaches a conductive structure over the transistor and the assembly in the first direction (LIAW ¶¶0055,0058 and note first conductive gate material over the n-well region 150 and a second conductive gate material over the p-well region 160, which are similar to those of the gate electrode 132. Similarly, the conductive material or materials of at least one of the conductive gate materials of the gate electrode 172 is/are selected in accordance with the type of device or transistor.).
As of Claim 5: LIAW in view of Huang further teaches an additional conductive structure, wherein the transistor is between the conductive structure and the additional conductive structure in the first direction (LIAW ¶¶0055,0058 and note each of the first and second conductive gate materials the gate electrode 172 includes a second conductive work function layer and a second contact layer over the second conductive work function layer. Properties and configurations of the second conductive work function layer and the second contact layer of the gate electrode 172 may be similar to those of the first conductive work function layer and the first contact layer of the gate electrode 132.) .
Claims 6&7 are rejected under 35 U.S.C. 103 as being unpatentable over LIAW (US 20190287967 A1) in view of Huang et al. (US 20220130765 A1; hereafter Huang), and further in view of JEON et al. (US 20140091366 A1; hereinafter JEON).
As of Claim 6: JEON is a similar or analogous system to the claimed invention as evidenced JEON teaches semiconductor devices and/or methods of manufacturing the same, and more particularly, to semiconductor devices including transistors and/or methods of manufacturing the same that would have prompted a predictable variation of LIAW by applying JEON’s known principal of the source region or the drain region is in a first support structure (¶¶0074-0075), the first semiconductor region or the second semiconductor region is in a second support structure, and the second support structure is over the first support structure in the second direction (FIGS. 2,4,6 and note that the substrate SUB11 may have a structure in which a plurality of unit substrates are stacked, that is, a multi-substrate structure. That is, the substrate SUB11 may have the same structure as or a similar structure to the substrate (or multi-substrate structure) SUB100 of FIGS. 2 and 4.).
In view of the motivations such as unnecessary interconnections may be omitted or the length of interconnections may be reduced as disclosed in ¶0151 of JEON thereby further making the integrated device more compact and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of LIAW.
Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
As of Claim 7: LIAW in view of Huang in view of JEON further teaches the dielectric structure comprises nitrogen (¶0107 of JEON).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEKONNEN D DAGNEW whose telephone number is (571)270-5092. The examiner can normally be reached on 8:00AM-5:00PM M-Th.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MEKONNEN D DAGNEW/Primary Examiner, Art Unit 2638
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