DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A discussion of the prior art rejection for the claims will begin with claims 15-18, 20, followed by claims 7-14 and 19, then followed by claims 1-6.
Claims 15-18, 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by EP 4086910 A1 Jiang et al. (hereinafter “Jiang”).
Regarding claim 15, Jiang discloses a method comprising:
storing multibit weight data ([0028] weight value – [0011]) to a memory array (Fig. 1 “102” [0028]);
conducting, by a capacitor ladder network (Fig. 1 “112” contains holding capacitors that form a C-2C ladder [0031] as exemplified Fig. 6 [0043], and further connected to Fig. 7 “702” [0065] found in the converter Fig. 7 “700” (Fig. 1 “114 [0031])), multiply-accumulate (MAC) operations ([0031]) on first analog signals ([0028] input value – [0011]) and the multibit weight data ([0028] weight value – [0011]);
outputting, by the capacitor ladder network, second analog signals based on the MAC operations (Fig. 1 “112” output to “114” [0031] final result), wherein the capacitor ladder network is external to the memory array (Fig. 1 “102” separate from “112” [0031] where each column of bitcells correspond with a separate holding capacitor disposed at the end of the column and included in the S&H circuit “110”).
Regarding claim 16, the teachings addressed in claim 15 analysis and rejection are incorporated, and Jiang discloses wherein:
selectively activating, by a controller (Fig. 7 “706” [0065]), a plurality of switches (Fig. 7 set of switches [0066-0067]) in the capacitor ladder network (Fig. 7 “702” [0065]) based on a data format of the multibit weight data ([0067] comparator “704” compares reference voltage with output from Fig. 6 “606”
V
O
U
T
[0063] where
V
O
U
T
represents the full MAC results for the entire 8-bit weight).
Regarding claim 17, the teachings addressed in claim 16 analysis and rejection are incorporated, and Jiang discloses wherein:
the plurality of switches includes a plurality of switch pairs (Fig. 7 switches in first position (to ground) and in second position (not to ground) [0065-0067]), and wherein each switch pair corresponds to one of the second analog signals (Fig. 7 switches final positioning corresponding to MAC result ([0065-0067]).
Regarding claim 18, the teachings addressed in claim 16 analysis and rejection are incorporated, and Jiang discloses wherein:
the data format includes one of an eight-bit integer format ([0011], [0029]) or a four-bit integer format ([0029]).
Regarding claim 20, the teachings addressed in claim 15 analysis and rejection are incorporated, and Jiang discloses wherein:
the memory array (Fig. 1 “102” [0028]) includes a static random access memory (Fig. 2 “202” [0032]) and the capacitor ladder network includes a C-2C capacitor ladder network (Fig. 1 “112” contains holding capacitors that form a C-2C ladder [0031] as exemplified Fig. 6 [0043], and further connected to Fig. 7 “702” [0065] found in the converter Fig. 7 “700” (Fig. 1 “114 [0031])).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang in view of US 11500442 B2 Tran et al. (hereinafter “Tran”).
Regarding claim 7, Jiang discloses a semiconductor apparatus comprising:
one or more substrates; and
logic ([0002], [0078], [0092]) coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware (Fig. 1 “100” [0028]), the logic including:
a memory array (Fig. 1 “102” [0028]) to store multibit weight data ([0028] weight value – [0011]); and
a capacitor ladder network (Fig. 1 “112” contains holding capacitors that form a C-2C ladder [0031] as exemplified Fig. 6 [0043], and further connected to Fig. 7 “702” [0065] found in the converter Fig. 7 “700” (Fig. 1 “114 [0031])) to conduct multiply-accumulate (MAC) operations ([0031]) on first analog signals ([0028] input value – [0011]) and the multibit weight data ([0028] weight value – [0011]), the capacitor ladder network further to output second analog signals based on the MAC operations (Fig. 1 “112” output to “114” [0031] final result), wherein the capacitor ladder network is external to the memory array (Fig. 1 “102” separate from “112” [0031] where each column of bitcells correspond with a separate holding capacitor disposed at the end of the column and included in the S&H circuit “110”).
Although Jiang discloses the logic, they appear to be silent to explicitly disclose one or more substrates coupled to logic.
Tran discloses one or more substrates (Fig. 2 – 7 “12”, co. 4 ln. 29-41) coupled to (Fig. 2 – 7 “12”, co. 28 ln. 54-59) logic.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Jiang’s semiconductor apparatus with substrate features as disclosed by Tran’s features because they are in the claimed invention’s same field of endeavor of memory architectures (co. 4 ln. 20-22). Modifying with Tran’s substrate feature would have been obvious to one of ordinary skill in the art as substrate is a common component in CMOS technologies and well known in the art in memory fabrication (co. 4 ln. 24-41). Using Tran’s well-known feature to yield a predictable result of memory manufacturing (co. 6 ln. 62-67, co. 7 ln. 1-5) before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Jiang’s semiconductor apparatus was ready for modification to incorporate the well-known feature, in addition to yielding the benefit of applying such fabrication methods to other types of memory technologies if needed (co. 6 ln. 62-67, co. 7 ln. 1-5).
Regarding claim 8, the teachings addressed in claim 7 analysis and rejection are incorporated, and Jiang discloses wherein:
the capacitor ladder network (Fig. 7 “702” [0065]) includes a plurality of switches (Fig. 7 set of switches [0065]) and the logic includes a controller (Fig. 7 “706” [0065]) to selectively activate the plurality of switches ([0066-0067]) based on a data format of the multibit weight data ([0067] comparator “704” compares reference voltage with output from Fig. 6 “606”
V
O
U
T
[0063] where
V
O
U
T
represents the full MAC results for the entire 8-bit weight).
Regarding claim 9, the teachings addressed in claim 8 analysis and rejection are incorporated, and Jiang discloses wherein:
the plurality of switches includes a plurality of switch pairs (Fig. 7 switches in first position (to ground) and in second position (not to ground) [0065-0067]), and wherein each switch pair corresponds to one of the second analog signals (Fig. 7 switches final positioning corresponding to MAC result ([0065-0067]).
Regarding claim 10, the teachings addressed in claim 8 analysis and rejection are incorporated, and Jiang discloses wherein:
the data format includes one of an eight-bit integer format ([0011], [0029]) or a four-bit integer format ([0029]).
Regarding claim 11, the teachings addressed in claim 7 analysis and rejection are incorporated, and Jiang discloses wherein:
the capacitor ladder network (Fig. 1 “112” contains holding capacitors that form a C-2C ladder [0031] as exemplified Fig. 6 [0043], and further connected to Fig. 7 “702” [0065] found in the converter Fig. 7 “700” (Fig. 1 “114 [0031])) and the second analog signals (Fig. 1 “112” output to “114” [0031] final result).
Although Jiang generally discloses multiplexers as part of a post processing segment in the circuitry (Fig. 8 “A1-A3” [0071]), this appears to be performed after the entirety of the CIM modules (Fig. 8 “100” [0070]) have been completed. However, an analog to digital converter (Fig. 1 “114” [0031]) is part of the complete CIM modules processing, and thus the signals which are processed in the multiplexers and “806” are digital signals, rather than analog. Therefore, Jiang appears to be silent to disclosing: a plurality of partial output activation lines to carry the second analog signals; and one or more multiplexers coupled to the plurality of partial output activation lines, the one or more multiplexers to combine the second analog signals.
Tran discloses a plurality of partial output activation lines to carry (Fig. 30 “BL0-BLN” co. 16 ln. 13-15) the second analog signals; and one or more multiplexers (Fig. 32 “3205” co. 16 ln. 27-40) coupled to the plurality of partial output activation lines (Fig. 30 “BL0-BLN” co. 16 ln. 13-15), the one or more multiplexers to combine (Fig. 32 “3205” co. 16 ln. 27-40) the second analog signals.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Jiang’s semiconductor apparatus with activation lines and multiplexer features as disclosed by Tran’s because they are in the claimed invention’s same field of endeavor of neuron VMM array architectures (co. 8 ln. 22-38). Modifying with Tran’s activation lines feature would have been obvious to one of ordinary skill in the art as activation lines are a well-known component in memory architectures and doing so would have yielded the predictable result of signal transmission (Fig. 2 – 7 “24”, co. 4 ln. 24-41). Further, modifying with Tran’s multiplexer feature would have been obvious to one of ordinary skill in the art as a part of the components required for gathering and outputting the signals, and doing so would have yielded the predictable result of combining (Fig. 32 “3205, 3206, 3207, 3208” co. 4 ln. 27-44). Using Tran’s features to yield a predictable result of transmitting and combining signals before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Jiang’s semiconductor apparatus was ready for modification to incorporate the features, in addition to yielding the benefit of processing the analog signals from the activation lines and outputting for further post-processing or computations (co. 4 ln. 27-44).
Regarding claim 12, the teachings addressed in claim 7 analysis and rejection are incorporated, and Jiang discloses wherein:
the memory array (Fig. 1 “102” [0028]) includes a static random access memory (Fig. 2 “202” [0032]).
Regarding claim 13, the teachings addressed in claim 7 analysis and rejection are incorporated, and Jiang discloses wherein:
the capacitor ladder network includes a C-2C capacitor ladder network (Fig. 1 “112” contains holding capacitors that form a C-2C ladder [0031] as exemplified Fig. 6 [0043], and further connected to Fig. 7 “702” [0065] found in the converter Fig. 7 “700” (Fig. 1 “114 [0031])).
Regarding claim 14, the teachings addressed in claim 7 analysis and rejection are incorporated, and Jiang discloses wherein:
the logic ([0002], [0078], [0092]).
Jiang appears to be silent to disclosing coupled to the one or more substrates includes transistor regions that are positioned within the one or more substrates.
Tran discloses coupled to the one or more substrates (co. 28 ln. 54-59 “12”) includes transistor regions that are positioned (co. 4 ln. 29-41 “18”) within the one or more substrates (co. 4 ln. 29-41 “12”).
The motivation to combine provided with respect to claim 7 similarly applies.
Claim 19 is directed to a method that would be performed by the apparatus of claim 11. The claim 11 analysis similarly applies and claim 19 is similarly rejected.
Claims 1-6 are directed to a system that recites similar limitations that would be performed by the apparatus of claims 7-13, respectively, where claims 12-13 both recite claim 6. The claim 7-13 analysis similarly applies and claims 1-6 are similarly rejected. In addition, claim 1 recites: a network controller, and a processor coupled to the network controller, the processor including logic.
Jiang discloses a network controller (Fig. 9 “906” [0076]), and a processor (Fig. 9 “914” [0078]) coupled to the network controller, the processor including logic ([0002], [0078], [0092]).
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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