Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/19/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 9-13 and 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jeong (Pub. No.: US 2025/0048853).
PNG
media_image1.png
686
1032
media_image1.png
Greyscale
Re claim 1, Jeong FIG. 4 [as shown above] teaches an electronic device, comprising:
a substrate (101);
a first gate line (G1) disposed on the substrate;
a first insulating layer (113) disposed on the first gate line;
a second insulating layer (115) disposed on the first insulating layer;
an oxide semiconductor layer (material of AO4) disposed between the first insulating layer and the second insulating layer;
a second gate line (G4) disposed on the second insulating layer (115);
a third insulating layer (116) disposed on the second gate line;
a first conductive element [CE] disposed on the third insulating layer;
a driving circuit (T1); and
a connection line (CL3);
wherein the first conductive element [CE] is electrically connected to the first gate line (G1) by passing through the first insulating layer (113), the second insulating layer (115) and the third insulating layer (116) and is electrically connected to the second gate line (G4) by passing through the third insulating layer;
wherein the driving circuit comprises a transistor (T1, note that “a driving range of a gate voltage applied to the first gate electrode G1 may be widened”, [0096], and G1 belong to T1), the connection line (CL3) is electrically connected to a source (S1, note that when the T1 is ON state, CL3 is electrically connected to the source S1) or a drain of the transistor of the driving circuit (T1) and the first conductive element [CE], wherein the substrate comprises an active region (A04) and a peripheral region [PR] adjacent to the active region [AR], the driving circuit (T1) is disposed in the peripheral region, and the oxide semiconductor layer (material of A04) is disposed in the active region [AR].
Re claim 3, Jeong FIG. 4 teaches the electronic device as claimed in claim 1, wherein the first insulating layer has a first opening (occupied by contact hole 14 surrounded by 113, [0109]), the second insulating layer has a second opening (occupied by contact hole 14 surrounded by 114), the third insulating layer has a third opening (occupied by contact hole 14 surrounded by 116), in a cross-sectional view of the electronic device, the third opening overlaps the first opening and the second opening, and the first conductive element (CL3) is electrically connected to the first gate line (G1) through the first opening, the second opening and the third opening.
Re claim 4, Jeong FIG. 4 teaches the electronic device as claimed in claim 3, wherein there is more than one first opening (occupied by contact hole 11 surrounded by 113), there is more than one second opening (occupied by contact hole 11 surrounded by 114), and there is more than one third opening (occupied by contact hole 11 surrounded by 116).
Re claim 5, Jeong FIG. 4 teaches the electronic device as claimed in claim 1, wherein the third insulating layer has a fourth opening (13), and the first conductive element [CE] is electrically connected to the second gate line (G4) through the fourth opening.
Re claim 6, Jeong FIG. 4 teaches the electronic device as claimed in claim 5, wherein there is more than one fourth opening (12/13).
Re claim 7, Jeong FIG. 4 teaches the electronic device as claimed in claim 1, wherein the oxide semiconductor layer comprises indium gallium zinc oxide (IGZO) [0134].
Re claim 9, Jeong FIG. 4 teaches the electronic device as claimed in claim 1, wherein the connection line (said copper material of CL3, [0144]) has a conductivity greater than that of the first gate line or the second gate line (said titanium material of gate electrodes, [0126]).
Re claim 10, Jeong FIG. 4 teaches the electronic device as claimed in claim 1, wherein, in a top view of the electronic device, the connection line (vertical width of CL3) has a width larger than that of the first gate line (vertical width of G1) or the second gate line (vertical width of G4).
Re claim 11, Jeong FIG. 4 teaches the electronic device as claimed in claim 1, wherein, in a cross-sectional view of the electronic device, the connection line (vertical width of CL3) has a thickness larger than that of the first gate line (vertical width of G1) or the second gate line (vertical width of G3).
Re claim 12, Jeong FIG. 4 teaches the electronic device as claimed in claim 1, wherein the driving circuit comprises a gate on panel (GOP) (G4 on 113).
Re claim 13, Jeong FIG. 4 teaches the electronic device as claimed in claim 1, wherein the transistor (T1) has a semiconductor layer (material of AS1).
Re claim 15, Jeong FIG. 4 teaches the electronic device as claimed in claim 1, wherein the connection line (CL3) is disposed above the second gate line (G4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of BANG (Pub. No.: US 2025/0098459).
Jeong teaches all the limitation of claim 8.
Jeong fails to teach the limitation of claim 14.
BANG teaches wherein the semiconductor layer comprises low-temperature polycrystalline silicon (LTPS) [0228].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving the turn-on characteristic as taught by BANG, [0228].
Response to Arguments
Applicant' s arguments with respect to claims 1-7 and 9-15 on the remarks filed on 08/19/2026 have been considered but are not persuasive because Jeong FIG. 4 [as shown above] still reads on: wherein the driving circuit comprises a transistor (T1, note that “a driving range of a gate voltage applied to the first gate electrode G1 may be widened”, [0096], and G1 belong to T1), the connection line (CL3) is electrically connected to a source (S1, note that when the T1 is ON state, CL3 is ELECTRICALL connected to the source S1) or a drain of the transistor of the driving circuit (T1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TONY TRAN/Primary Examiner, Art Unit 2893
Prosecution Insights