Prosecution Insights
Last updated: April 19, 2026
Application No. 18/188,089

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §103§112
Filed
Mar 22, 2023
Examiner
NGUYEN, DUY T V
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Renesas Electronics Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
828 granted / 1052 resolved
+10.7% vs TC avg
Strong +17% interview lift
Without
With
+17.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
57 currently pending
Career history
1109
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
51.5%
+11.5% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
14.2%
-25.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1052 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Election/Restrictions 1. Applicant’s election without traverse of Group I, claims 1-8 in the reply filed on 8/5/2025 is acknowledged. Specification 2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 3. Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: a dielectric film IN (refer to Fig. 3, page 7, 2nd par.). For best understanding and examination purpose, the claim(s) will be best considered based on drawings, disclosure, and/or any applicable prior arts. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 3. Claim(s) 1-3 and 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda et al. (US 6,465,832) in view of Inbe (US 2004/0043556). Re claim 1, Maeda teaches, under BRI, Figs. 28-29, cols. 9-10, a semiconductor device comprising: -a first electrode (flat electrode 7a) and a second electrode (flat electrode 7b) configuring a capacitor (e.g., structure of capacitor), wherein the first electrode (7a) includes a first via plug (through hole 10 filled with metal) extending along a first direction (z axis) in plan view, wherein the second electrode (7b) includes a first wiring (3a or 3b) extending along the first direction (z axis) in plan view and arranged side by side with the first via plug (10) in a second direction (y axis) orthogonal to the first direction, wherein a length of the first via plug (10) in the first direction (z axis) is larger than a length of the first via plug (10) in the second direction (y axis), wherein a length of the first wiring (3a or 3b) in the first direction (z axis) is larger than a length of the first wiring (3a or 3b) in the second direction (y axis). PNG media_image1.png 725 537 media_image1.png Greyscale Maeda does not explicitly teach wherein a thickness of the first via plug in a third direction orthogonal to each of the first direction and the second direction is larger than a thickness of the first wiring in the third direction. Inbe teaches, Fig. 1, [0027-0028], a thickness of the first via plug (1a-c) in a third direction (x axis) orthogonal to each of the first direction (z axis) and the second direction (y axis) is larger than a thickness of the first wiring (3) in the third direction (x axis). As taught by Inbe, one of ordinary skill in the art would utilize & modify the above teaching to obtain a thickness of the first via plug in a third direction orthogonal to each of the first direction and the second direction is larger than a thickness of the first wiring in the third direction as claimed, because a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Inbe in combination with Maeda due to above reason. Re claim 2, Maeda teaches, Fig. 28, a first dielectric layer (2) arranged on the first wiring (3a or b), wherein the first via plug (10) penetrates the first dielectric layer (2). Re claim 3, Maeda teaches, Figs. 28-29, a second dielectric layer (2b) arranged on the first dielectric layer (2a); and a second via plug (6 or 9) extending along the third direction (x axis) from an upper surface of the first wiring (3a, b) and arranged side by side with at least part of the first via plug (10) in the second direction (y axis), wherein the second via plug (6 or 9) penetrates the second dielectric layer (2b). Re claim 6, Maeda teaches, Fig. 28, a third wiring (7a) and a fourth wiring (3a) arranged spaced apart from each other in the third direction, the third wiring (7a) and the fourth wiring (3a) each extending along the first direction, wherein the first via plug (10) electrically connects between the third wiring (7a) and the fourth wiring (3a). Re claim 7, in combination cited above, Inbe teaches, Fig. 5, [0043-0044], an etching stopper film (insulating film 112) in contact with one end of the first via plug (13a, 14) in the third direction. Re claim 8, Maeda teaches, Fig. 28, the length of the first via plug (10) in the first direction (z axis) is larger than the length of the first wiring (3a, b) in the second direction (y axis). 4. Claim(s) 1, 4-6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coolbaugh et al. (US 2007/0190760) in view of Inbe (US 2004/0043556). Re claim 1, Coolbaugh teaches, under BRI, Fig. 5, abstract, [0021-0022], a semiconductor device comprising: -a first electrode (lower 52) and a second electrode (upper 52) configuring a capacitor (e.g., parallel plate capacitor), wherein the first electrode (lower 52) includes a first via plug (53) extending along a first direction (y axis) in plan view, wherein the second electrode (upper 52) includes a first wiring (indicated) extending along the first direction (y axis) in plan view and arranged side by side with the first via plug (53) in a second direction (x axis) orthogonal to the first direction, wherein a length of the first via plug (53) in the first direction (y axis) is larger than a length of the first via plug (53) in the second direction (x axis). PNG media_image2.png 347 545 media_image2.png Greyscale Coolbaugh does not explicitly teach wherein a length of the first wiring in the first direction is larger than a length of the first wiring in the second direction, and wherein a thickness of the first via plug in a third direction orthogonal to each of the first direction and the second direction is larger than a thickness of the first wiring in the third direction. Inbe teaches, Fig. 1, [0027-0028], a length of the first wiring (3) in the first direction (x axis) is larger than a length of the first wiring (3) in the second direction (y axis), and wherein a thickness of the first via plug (1a-c) in a third direction (z axis) orthogonal to each of the first direction and the second direction is larger than a thickness of the first wiring (3) in the third direction. As taught by Inbe, one of ordinary skill in the art would utilize & modify the above teaching to obtain a length of the first wiring in the first direction is larger than a length of the first wiring in the second direction, and a thickness of the first via plug in a third direction orthogonal to each of the first direction and the second direction is larger than a thickness of the first wiring in the third direction as claimed, because a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Inbe in combination with Coolbaugh due to above reason. Re claim 4, Coolbaugh teaches, Fig. 5, the second electrode includes a second wiring (indicated) extending along the first direction and arranged side by side with the first via plug (53) in the second direction, and wherein the first wiring (indicated) and the second wiring (indicated) are arranged so as to sandwich the first via plug (53). Re claim 5, Coolabaugh teaches, Fig. 5, a potential of the first wiring (indicated) is equal to a potential of the second wiring (indicated) (both connected to upper 52). Re claim 6, Coolbaugh teaches, Fig. 5, a third wiring (lower 52) and a fourth wiring (higher 52) arranged spaced apart from each other in the third direction, the third wiring (lower 52) and the fourth wiring (higher 52) each extending along the first direction, wherein the first via plug (53) electrically connects between the third wiring and the fourth wiring. Re claim 8, Coolbaugh teaches, Fig. 5, the length of the first via plug (via 53) in the first direction (y axis) is larger than the length of the first wiring (indicated) in the second direction (x axis). Conclusion 5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/21/25
Read full office action

Prosecution Timeline

Mar 22, 2023
Application Filed
Oct 01, 2025
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+17.1%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 1052 resolved cases by this examiner. Grant probability derived from career allow rate.

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